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Cypress continues to expand it's portfolio of Low Power SRAM's with a 128 Mbit SRAM (4Mb x 32 configuration). The part is called CY62192ESL. Production ramp is expected from October 2011.

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Ultra Low Power SRAMs also called as More Battery Life (MoBL) have made their way into various applications-

mobile phones, PDAs, Point of Sale (POS) terminals and pacemakers etc. Most of the applications use a Battery 

and an SRAM to store critical data in case of power failure. The critical data is stored in the SRAM powered 

by a battery. Hence,low standby power is a critical requirement for the MoBL SRAM. Battery backed 

applications are used extensively due to low cost-simple-quick-to-market system solutions. Over the years due 

to the advantage of technology/device scaling, easy migration happened from 250nm to 90nm for MoBL SRAMs. For 

example 4M (Buswidth/Databits of 😎 MoBL Cypress SRAM in 250nm had speed of 70ns and ISB max of 20uA and the 

same 4M MoBL Cypress SRAM offered in 90nm has speed of 45ns and ISB max of 7uA under same conditions. Even 

before the device scaling happened, the need for faster data rates in these applications demanded more 

databits/Buswidth for MoBL SRAM. Thus,MoBL devices with Buswidth/Databits of 16 have emerged. And also over 

the years the need existed for large amount of critical data to be stored in these applications made to 

achieve huge memory (SRAM)arrays with the help of device scaling. Today in 90nm technology as high as 64M 

(Buswidth of x16) density is offered by Cypress. Now Cypress being the Market leader for these MoBL SRAMs; is 

truly committed to Customers in offering Best-In-Class MoBL SRAM devices and is constantly thriving hard to 

improve the specs for these MoBL SRAMs

The nvSRAM has a specified t_HRECALL (Power up RECALL duration) time for boot up / RECALL of data. When user powers up the device, at the end of the t_HRECALL period, the device is ready for access. Which means user can perform read/writes. The t_HRECALL completion is signaled at the HSB# (Hardware Store Busy) pin and user can start read/write based on HSB# going HIGH in case user is monitoring HSB# pin. HSB# will go HIGH in <= t_HRECALL time. Since there is no restriction on what user can do after the part is ready, let us say user performs a write as soon as the part completes the power up RECALL and immediately powers down the part (planned on unplanned power down). The device will perform an AutoStore using the charge from the V_CAP pin and it is guaranteed that the AutoStore will be successful under this condition also.

If user now has a capacitor on V_CAP pin which is outside the spec, consider a 330uF which is higher than the datasheet spec limit of 180uF max, the capacitor would have charged to a lesser voltage than what would be the level if 180uF was on the pin. This would affect the AutoStore operation completion as described below.

During power down, when the V_CC crosses V_SWITCH, the power to the internal store circuit switches to the V_CAP pin. From then on V_CAP charge provides the power required to complete the AutoStore. Assume V_SWITCH for the part is 2.4V and the store circuit needs to have a minimum voltage of 2.0V on V_CAP to complete the STORE, then the capacitor value should be such that it accumulates enough charge on it to complete the AutoStore operation in t_STORE time (8 ms) while it discharges from 2.4 V to 2.0 V. In the case of higher capacitor, the starting voltage would be lower (since it was charged for the same t_HRECALL time from the same internal charging circuit). However it still may accumulate sufficient charges to complete the AutoStore in time which is determined by the value of capacitor and its voltage level above 2V. On the worst case side, assume the capacitor did not even reach 2V because the capacitor value is too high. Then there will be a complete failure of AutoStore. Therefore, the higher value spec for V_CAP is specified to guarantee that AutoStore will be successful if it is required to be done as soon as at the end of t_HRECALL (= 20ms). If user still needs to use 330uF, user needs to ensure that AutoStore is not going to be required immediately after power up and ensure that there is sufficiently longer time before performing a write operation. (If there is no write operation after a NV operation, there will be no initiation of AutoStore since the NV data is same as the SRAM data). That is, give additional power up time before starting access, say add 20ms more before starting access.

Also note that the typical value mentioned in the datasheet is the minimum cap value with 10% tolerance which will ensure AutoStore will always be completed for any part across PVT (Process, Voltage, Temperature) range. And minimum value is the value net of tolerance (the minimum absolute value) which will ensure that AutoStore is successful across PVT. Please note that the performance of the part is the same if any value of capacitor across the min to max specification is used.

A nvSRAM memory cell integrates a fast access SRAM cell and a non volatile NV cell in a monolithic die. This cell structure offers the benefit of high performance SRAM access and non volatility of EEPROM/FLASH. In a typical system configuration where the system controller uses external memories for storing its firmware program and data, a Flash memory is used to store the program code and a SRAM is used to store runtime data and variables. During system boot up, the firmware code is first dumped into SRAM from the flash and then executes from SRAM. 

S ince the nvSRAM combines SRAM and NV cells, it can potentially replace the combination of SRAM and FLASH with a single memory. After a power cycle, the data stored in NV cells of nvSRAM is available to SRAM after 20 ms (Power up Recall duration) which can be used by the controller for its boot up process. Once boot up process completes, the same SRAM space can be used as data memory for storing run time variables, parameters and scratch pad data.  In this used model, the AutoStore feature of nvSRAM must be disabled so that SRAM data is never written back to its NV cell on its own by performing an AutoStore cycle. This will ensure that NV portion always stores the F/W program code. Disabling AutoStore features makes NV memory in nvSRAM as read only memory (ROM). To program the nvSRAM again with a new F/W code and store in its NV cell, on demand Software Store command can be issued which will Store a new code into its NV cell.

The only drawback with this approach is that data is not available in the SRAM for the first 20 ms during power up RECALL duration. It means controller boot up will start only after 20 ms.  After 20 ms entire program memory is available in SRAM, whereas in SRAM+Flash combination, controller initially copies code from the program memory (Flash) to data memory (SRAM) on byte by byte basis.   

Hi All,

The new serial nvSRAM RTC devices can be used to detect less than a second using its newly added Square Wave generation feature. nvSRAM RTC devices can generate Square wave of  frequencies 1 Hz, 512 Hz, 4096 Hz and 32768 Hz on INT pin. This along with RTC time keeping registers can be used to count less than a second.

Regards,

Harsha