Why is the power-on reset bit of the global status byte active low at the TLE92104 and TLE92108?
Unlike the other status bits of the global status byte, the (negated) power-on reset (NPOR) bit is active low:
- NPOR = 0 after a power-on reset of the device. NPOR stays 0 until GENSTAT is cleared
- NPOR = 1 if GENSTAT is cleared
The arbitrary polarity definition of this bit allows the microcontroller to detect a shorted SDO line to GND: After a clear command on GENSTAT, NPOR should be 1(the power on-reset is “cleared”), unless SDO is shorted to GND.
If the SDO line is shorted to GND or the device is in sleep mode, then the microcontroller reads NPOR = 0, despite the attempt to clear the GENSTAT register.
Note: The microcontroller can detect a short circuit to VDD if the most significant bit (MSB) of the Global Status Register is set. Indeed, according to the SPI protocol of the TLE92108/4, the MSB of the Global Status Register must be 0, unless the SDI line is shorted to VDD.
