I am using the IAUC45N04S6N070HATMA1 half-bridge in a design and am using the suggested footprint from the datasheet.  The suggested footprint has keepout areas between what appears to be thermal pads and the associated pins on the part.   I can see from the bottom image of the part that those "thermal pads" are actually connected to pins.

It would simplify the PCB routing significantly if I can route directly to the the "thermal pad" that is connected to pins 2 and 3 instead of routing directly to pins 2 and 3.  Would this be a problem?

Do you have an example PCB layout from maybe one of your reference designs that uses a half-bridge in the PG-TDSON-8-57 package?

Thanks, David

Hi,

I am currently working on PLECS Simulink platform about an inverter model using your SiC MOSFET PLECS model (IMZA120R020M1H), I am quite confused about the conduction loss in the thermal model, hense I have 2 questions about this thermal model.

1. Just as the following picture 1 shows that the Von of Forward MOSFET und Reverse MOSFET is same, considering the effects of bodydiode inside MOSFET it is usually that the Von of Forward MOSFET und Reverse MOSFET should be at least a little different, right? As far as I see, the Von of Reverse MOSFET should be a little lower than Foward MOSFET, since the Ron of Reverse channel is lower.

2. Since the PLECS thermal model type is "MOSFET with Diode", so the conduction loss should be a total conduction losses of MOSFET and bodydiode. And if there is not positive gate signal for MOSFET, the reverse conduction channel should only be bodydiode, right? However unfortually it seems that the thermal model has mixed the Reverse MOSFET channel and bodydiode channel. It is sad that I can't upload my plecs model in the attachment, so you can figure out my problem clearly. The problem is when there is no positive gate signal for S5/S6 MOSFET (shown in picture 2), it still works in the Reverse channel of MOSFET, due to no extra bodydiode channel for current to conduct. For this problem, can you give me a suggestion to fix it? Or do you maybe have the newest correct PLECS model that can help me solve this problem?

Thanks a lot for your answer and help!

Best regards

Joy

Hi, can I read a shunt placed like this? I need to share this shunt with another IC and this location is mandatory.

Thanks!

IAUA250N04S6N006

Is the graph already adjusted for temperature? It appears RDS(on) in the left margin is the value for each temperature, correct?

IQDH45N04LM6CG

Table is slightly different identifies the left margin as RDS(on) (normalized to 25C) and would require the respective value on the left of the graph to be multiplied by RDS(on), Max, to get the resulting RDS(on) at the respective temperature, correct?