MOSFET (Si/SiC) Forum Discussions

HI all, new to the forum so I apologize if this repeats similar posts.

I have a design that needs to switch high power to drive LEDs for short pulses.

The voltage to the LED string is 45V and the current is a maximum of 24A.

the pulsewidth is 5mS and the overall pulse-train frequency is 5 Hz.

I am looking at using the IAUZ40N06S5L050.  this FET is at the bottom of the string and according to LTSpice sees only about 24V for Vds.  So the question is, according to the datasheet, this is a bit outside of the safe zone but only slightly,  I am restricted to very small space so the package/footprint is a good fit.  Will this work?

Hello,

IRFP044NPBF is discontinued, I found IRFP064NPBF, can I use it to replace the IRFP044NPBF ?

My project uses this mosfet as an electronic load for 20V, 3A, 60W max.

Hi Infineon friends.

Hello!

Does OptiMOS 5 offer a power cycling curve? (IPT015N10N5)?

Is there a way to determine that the number of cycles corresponding to ∆T has exceeded the part's capacity if it breaks down early in the life test?

Thank you!

IPT015N10N5

Best Regards.

Jay.

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I built a high-voltage low-power DCDC prototype with symmetrical half-bridge topology using the IMBF170R650M1. Due to the extremely small Id (only 30mA), only the capacitive turn-on loss caused by Coss charging and discharging was taken into account when calculating the loss of the IMBF170R650M1. However, it was found in the experiment that the actual loss value is much larger than the calculated value according to the datasheet.

Please guide me to calculate the loss of IMBF170R650M1 under experimental conditions (100kHz, DC voltage Vds=1000V, drain current Id=30mA, symmetric half bridge topology).

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Hi,

We are experiencing clamping problems when using the 1ED3461MU12M to drive the MOSFET IMYH200R075. The circuit is as follows: CH3 (upper tube) and CH4 (lower tube) conduct at the same time, CH2 is the lower tube of the other set of bridges do not conduct at this time. The effect on the Vgs signal of the lower CH2 (off) is verified by the dv/dt generated at the corresponding node when the upper CH3 is on. The load is purely resistive.

The driver circuit diagram is shown above.

Vgs signal test circuit diagram as above.

When the bus voltage is about 950V, the test results are as follows: the blue color is the Vgs signal of the lower tube of CH2, and the purple color is the current signal of IR. From the figure, we can see that the negative voltage of Vgs turns off CH2, and during the simultaneous conduction of CH3 and CH4, Vgs receives a spike due to the influence of dv/dt, with a positive spike peak of about 7.5V and a negative spike peak of about 10V.

According to the IMYH200R075M1H datasheet its Vgs cannot exceed -10V while its conduction threshold is about 3.6V.

So there are a couple questions I need to ask:

1. Is there a finite value for the duration corresponding to the transient voltage of Vgs of IMYH200R075M1H? For example, if the duration of Vgs >10V is greater than 100ns, the MOSFET will be damaged.
2. In the graphic of the test Vgs waveform Vgs forward spike exceeds the threshold of 3.6V, is the CH2 lower tube parasitically conducting at this time?
3. In the graph of the test Vgs waveform, the negative spike of Vgs reaches 10V. If I continue to increase the bus voltage to 1200V, the negative spike of Vgs may be more than 10V, will it cause damage to the MOSFET?
4. According to the test waveform of Vgs, it seems that the clampdrv of the driver chip is not working properly, check the description of the clampdrv: the clamp filter time is about 235ns, while the actual test waveform of the Vgs spike pulse lasts about 100ns, is it related to the fact that the calmp function is not working properly?

If the above problem is the result of the clamp filter not responding in time, then there are still some questions about the test waveforms in the following article on active clamping:

https://community.infineon.com/t5/%E7%9F%A5%E8%AF%86%E5%BA%93%E6%96%87%E7%AB%A0/%E5%A6%82%E4%BD%95%E6%9B%B4%E5%A5%BD%E7%9A%84%E4%BD%BF%E7%94% A8EiceDRIVER-IC%E9%A9%B1%E5%8A%A8SiC-MOSFET/ta-p/499376

In the above graph, the waveform after clamping compared to the waveform before clamping does not show the spikes during the clamp filter time, it is logical that after the clamp filter, the clamp starts to act, so there will be spikes as well as spikes that can't be clamped during this period of time in the clamp filter. Is the above understanding correct?

Thank you very much, looking forward to a reply!

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3415STRLPBF Is the origin different face typing silkscreen is not the same, there is no written official instructions

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I need a couple demos (Simulink or PLECS) of DAB11KIZSICSYS or other isolated DCDC converters and would like to do some simulation experiments. Thanks #DAB11KIZSICSYS

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Hello.

I would like a Chinese version data sheet for IPC100N04S5-1R7

Only in English

Please provide it to me

thanks

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