MOSFET (Si/SiC) Forum Discussions

Hello, infineo engineers.

I load the IMBF170R650M1_L3 pspice model in cadence and report some errors. I review the model and find something suspectable.

.SUBCKT Z00XD 1 2 3 4 5 6 7 8
X0ZY7 1 2 3 4 9 10 11 12 Z01F2
X10WI 9 10 11 12 Z0590
X11CV 9 10 11 12 5 6 7 8 Z01F2

is it missing ‘.ENDS Z00XD’？

.SUBCKT Z0590 1 2 3 4
C229H 1 0 3.12275E-13
C24YC 1 2 3.281062E-13
C26PC 1 3 1.122796E-12
C26YG 1 4 2.436658E-13
C27QW 2 0 6.827946E-14
C2ANY 2 3 7.051034E-14
C2BMM 2 4 3.883722E-13
C2BSK 3 0 1.7097006E-13
C2FCQ 3 4 4.306726E-13
C2GI4 4 0 3.29534E-14
.ENDS Z0590
.ENDS Z00XD

is '.ENDS Z00XD' in the wrong line?

Hello,

IAUS260N10S5N019T is my synch rectifier switch at secondary side of circuit as parallel configuration. You can see at below. When I am starting to switch, current waveform is getting quite high than normal value. I could't understand why this amount of current flows because my output current is 28A normally. Primer side switch is also Infineon which is IMBG65R048M1H. 

When I disable to SR and prefer to use body diode of IAUS260N10S5N019T, everything is working properly as expected. Problem starts when SR is enabled. Driver model is UCC21530 in simulation. You can see the current waveform at below, lower one when SR actived, upper one when SR deactived which is normal one. Only this parameter change in simulation.

I have also tried different Infineon switch model to see the effect, same issue happen. Could you please evaluated that is there any problem about LTspice model? Because I couldn't understand this kind of behaviour. Could you please support to understand this issue?

If you need any more information please feel free to ask.

BR,

Tevhide

Hi, I'm planning to use the IPT010N08NM5 with a high side FET controller to push 30A+ into my design. The ambient temp will be in the 110-120C range. Is there any way to review the PCB layout to make sure I'm pulling enough thermal energy off the FET and into the chassis?

I received how many seconds tp(pulse time) is about FF6MR12KM1(1200V/6mΩ/250A).  ID pulse is 500A.

It's only described as "verified by design, tp limited by Tvjmax" in data sheet, no more information about tp of pulsed drain current.

I'd like to know whether there is the way to calculate the pulse time for pulsed drain current.

Is there such way?

Regards,

Hi, it is my first time to use SiC Mosfets and 2ED020I12-F2. And I have some questions, they may be basic but they are very important to me. I very much look forward to getting your response.
(1)In the example of EVAL_2ED020I12-F2, part of the schematic diagram is shown in Figure 3-3. The values of D2B and D3B are BAT165, and they are Schottky diodes after checking. But why are they drawn as zener diodes?
(2) Also in Figure 3-3, C3B is important in desaturation protection. In the example of EVAL_2ED020I12-F2, 2ED020I12-F2 is used to drive IGBT-IKP20N60H3, whose short circuit withstand time is 5 μs when VGE = 15V. Is the short circuit response time calculated as "Vdesat/Idesatc*C3B + Tdesatleb +Tdesatout = 9V/500μA*220pF + 400ns + 350ns = 4.71 μs" ? Then, since 4.71 μs is less than 5 μs, the design of C3B is reasonable. My question is, is the value of 220pF for C3B still reasonable when I use 2ED020I12-F2 to drive SiC Mosfet instead of IGBT? For example, when the short circuit withstand time of a certain type of SiC Mosfet is 3 μs, should the value of C3B be changed to 110pF so that the short circuit response time is 2.73μs?
(3) Also in Figure 3-3, RG1B and RG2B are designed to be 100 Ω, are their resistances too high? In the datasheet of IKP20N60H3, the recommended gate resistance is 14.6Ω.

Hello 

Can  2 modules be connected in parllel to achive 22 kW, if yes, can you just help with any precausions or issues that might arise from such a configuration.

The second question, if you need to scale this design to achive 22 kW , can you recommend the part numbers and the new  resonant compnent values? and can you still us the same GUI and available source to control the new design for testing purposes , is that something you can support 

Thank you

I have read the Datasheet.

https://www.infineon.com/dgdl/Infineon-FS03MR12A6MA1LB-DataSheet-v01_10-EN.pdf?fileId=5546d4627883d7e001788ce9d7125011

but I do not understand the positional tolerances marked with red boxes on the specification. I have the following three questions, and I would be extremely grateful if you could answer them for me:

1. Is it a composite positional tolerance?
2. Why is the tolerance in the second row larger than that in the first row?
3. What do the positional tolerances in the first and second rows represent, and why are they marked in this way?

Dear Sir,

regarding to TDSON-8FL(enlarged source interconnection) package of soldering rules, and void rate, could provide me with related documents or suggestions?

  thanks.