MOSFET (Si/SiC) Forum Discussions
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The document has a graph of (Figure 9 Time evolution of PBTI at 200°C using a stress bias of +25 V.), but does this also occur when the temperature is below 100°C, etc.?
Please provide a graph of temperature-dependent characteristics, if any.
Also, how much do gate threshold voltage and ON resistance change with DC BTI?
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Hello, I have a few questions for you to answer, thank you!
1. Diagnosis enables DEN to be suspended or grounded when not in use
2. Is the relationship between IN_SET and OUT corresponding one by one
3. The role of VS foot and OUT foot connected to 4.7NF
4. When ST is the diagnostic output, can ST be connected together using the same lighting function of multiple devices
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/TLD2314EL/td-p/682659
Show LessI want to know about baking condition of BTF3035EJ
Hi, I hope you are doing well. I bought a full bridge MOSFET Power Module, F415MR12W2M1B76 (it seems to be a pressfit module). I have a query: Is there any full bridge evaluation board that can be directly mounted on the MOSFET Power Module F415MR12W2M1B76? If there is no direct-mounting full bridge evaluation board, then can you please guide me on how to connect the separate MOSFET power module and gate driver board, and what type of connector cables/strips/buses to use? Thank you for your valuable suggestions.
Data Sheet link of F415MR12W2M1B76:
https://www.infineon.com/dgdl/Infineon-F4-15MR12W2M1_B76-DataSheet-v02_00-EN.pdf?fileId=5546d4627956d53f01797a3e06e651f5
Hello, I would like to ask Infineon's opinion on the accuracy of LTSPICE simulations. Can the models and simulations and actual conditions provided on the official website be considered relatively accurate? It can still only be used to compare the advantages and disadvantages of the 2 devices #Optimos3 ~6
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Show Less1. When the N-MOSFET is completely turned off, when there is a single voltage pulse at both ends of the D-S pole, and the maximum value of the pulse exceeds the minimum value specified in the MOSFET specification. In such a scenario, when evaluating whether the MOSFET is at risk of voltage stress breakdown, is it necessary to look at the pulse width time of this single pulse? Still, there is no need to look at the pulse width time of the pulse; just determine whether the maximum value of the pulse exceeds the minimum value in the specification.
2. When browsing the MOSFET specification, I found that the voltage stress for VDS in the AOS specification, for example, would test a VDS SPIKE parameter; this parameter was not found in the IR specification. So when I use the IR BSZ018N04LS6 device, there will be a single pulse impact with a maximum value of 48V and a pulse width of 500ns at both ends of the D-S pole. In this case, how to determine whether the IR device will break down due to overvoltage according to the parameters in the specification. If I use an AOS device, I can evaluate it based on the parameter values of VDS SPIKE by considering the parameter items in the specification.
Examples of AOS specifications:
Example specifications using IR device models: No VDS SPIKE parameter items
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/MOSFET%E5%99%A8%E4%BB%B6%E7%9A%84%E7%94%B5%E5%8E%8B%E5%BA%94%E5%8A%9B%E9%A3%8E%E9%99%A9%E8%AF%84%E4%BC%B0-%E6%98%AF%E5%90%A6%E4%B8%8E%E5%8D%95%E6%AC%A1%E8%84%89%E5%86%B2%E7%9A%84%E8%84%89%E5%AE%BD%E6%97%B6%E9%97%B4%E6%9C%89%E5%85%B3%E7%B3%BB/td-p/681235
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