MOSFET (Si/SiC) Forum Discussions
I bought the following board mentioned in title. I have all the exclusive information. I want to know how the board regulates the voltage in BOOST mode? I want specific answer to it.Show Less
My post is about the IRAUDAMP23 evaluation board. It can provide 2x500W power ; my question is : is there a limitation to the 500W ? If yes, how is made this limitation and how to change this limit ?
Thank youShow Less
I'm currently comparing the Full-Bridge LLC (FB-LLC) and the Half-Bridge LLC (HB-LLC) and I'm wondering until when the usage of the HB-LLC makes sense.
HB-LLC has multiple advantages over FB-LLC. Especially when splitting the resonance capacitance Cr. This would apply more stress to the capacitance, but it also stabilizes the input dc-link voltage more. Additionally it would prevent incomplete body diode reverse recovery, which can damage the power FET due to large current caused by the high reverse recovery charge.
Therefore it seems that the HB-LLC is the more reliable and more forgiving topology.
The FB-LLC has the main advantage that it uses the whole input voltage Vin, when the HB-LLC only uses half of it Vin/2. This reduces the current stress on the components in the FB-LLC. Due to the lower current and the two more switches the heat dissipation would be less and more distributed.
With a combination of phase-shifting and frequency variation the input voltage range of the FB-LLC can be increased.
One issue in a full-bridge LLC relates to holding the input voltage bus constant enough not to effect the resonant waveforms. 
The formulas also indicate that a smaller Cr and Lm is needed in the FB-LLC, while the Lr gets bigger. This would decrease the resonance circuit, but the bridge would get bigger and more expensive due to the higher component count.
For a high power LLC converter (1.5kW) the appropriate topology would be the FB-LLC.
But when I run the numbers for the HB-LLC topology than the current of the equivalent load on the primary winding side is only 8.33A. The magnetizing current is 3.44A and the resonant current is 9.01A. These current stress values seem as manageable.
Am I missing something or is the HB-LLC here still a good choice?
Best regardsShow Less
Hello, I have a question abouot the Junciton-to-ambient thermal resistance of IRLR2908PbF MOSFET:
The datasheet specifies 40 °C/W referring to a note at the end of the document:
The note states that this value is valid "When mounted on 1" square PCB (FR-4 or G-10 Material)." It also says: "For recommended footprint and soldering techniques refer to application note #AN-994"
Here is my question: Is the note referring to a 1 in^2 copper pad below the device (as AN-994 recommends) or is it only the area of the PCB with the device mounted in a minimum footprint?
we have SIC MOSFET with Gate driver design and refer to the IFX web EVAL_3KW_50V_PSU.
Can you help us to review the schematic and also advise good component vales? thanks!
I have a doubt in 3.3kW PFC stage in the given Infineon code for 3.3kW PFC demo board. The VIN AC RMS voltage is calculation is done by using a digital filter . The Vin sensed ADC reading is sampled at 30kHz. The digital filter function is called every 2.5kHz. The output of filter is considered as average AC voltage . This average voltage is multiplied with 1.111 to get RMS AC voltage. I want to know the cutoff frequency and type of filter used.
Below the equation used in code for filter. g_U_in is the ADC reading for Vin Ac sense.
I am going to purchase some sample of IPN80R900P7 MOSFET for our LED lighting design project. But it is unable to source it in the current market. Any alternative component can be advised?
Hi, I notice that IFX released a series of mosfets with top-side-cooling package, such as TOLT, DDPAK and QDPAK. Since the top surface should be attached on the heatsink or cool plate, I wanna know how much stress(PSI unit) the package could endure and where to find the figures? Any application note is available on the website? thanksShow Less
そこで質問ですが、SpiceモデルではDriver SourceピンとPower Sourceピンが同じピンとしてモデリングされていますが、SW損失はDriver Sourceピンが存在しないため若干悪い結果になると考えてよろしいでしょうか？