SiC Mosfet for Soft switch Inverter topology

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harshagovind
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Hi ,

Application: Soft-switch H bridge Inverter

Switch required to operate 1.2 MHz, 20 A, Soft-switching (Resonant converter) where DC link voltage will be 400 Vdc. 

Can 650V SiC Mosfet operate at 1.2MHz switching frequency? Any considerations while operating at such frequency.

Thanks,

Harsh

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1 Solution
Pablo_EG
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First question asked 250 sign-ins 250 replies posted

Hello Harsh,

Thank you for posting on Infineon Community.

Q: Can 650V SiC Mosfet operate at 1.2MHz switching frequency?
A: Yes, it can be done.

Q: Any considerations while operating at such frequency?
A:

Qoss discharging
As it is a soft-switched topology, Qoss needs to be discharged to make sure the body diode turns on and soft switching happens.
The main drawback of SiC technology is the high body diode voltage drop, Vf. While for Si it is only about 1V, SiC's is 3.6V.
This means that the periods when the body diode is conducting should be minimized, for efficiency's sake.
Tdon, Tdoff, Tr, and Tf impact the deadtime that needs to be implemented.
When operating at high switching frequencies, the deadtime becomes more significant, as it takes a larger portion of the switching cycle.

dV/dT
Due to the need to charge the Coss, at startup and low loads, there is a risk of hard commutation.
Ensure that the gate driver is as close to the switches as possible to minimize the gate loop, as the high dV/dt could trigger unintended turn-on due to crosstalk.
SiC's output capacitance is more linear than Si, which allows for faster switching times with less overshoot.
However, make sure that the parasitic inductance of the power loop is minimized.
If a hard-switching event happens, the high dV/dt could induce a voltage spike which in extreme cases could go over the Vds_max parameter and make the switch go into avalanche.

Gate driving
SiC has different gate requirements than Si.
Unlike Si devices, SiC does not saturate at 20 Vgs, therefore an 18V Vgs is recommended for the lowest possible Rdson.
Due to the best-in-class Crss/Ciss ratio, the 650V CoolSiC devices can be turned off at 0V with minimal gate voltage spiking.
Keeping Vgs_min at 0V also has the added benefits of lower Vgh_th drift in time, which prevents the deterioration of the device.
If negative undershoots are a problem, a clamping diode can be used between the gate and source (or kelvin source) of the switch.

For further information on the CoolSiC technology and its utilization in soft-switching topologies, please refer to the following application note:

https://www.infineon.com/dgdl/Infineon-MOSFET_CoolSiC_650V_SiC_trench_power-ApplicationNotes-v02_00-...

Here, the following topics are discussed in detail, which could be relevant to your application.

Chapter 3: technology parameters
-Qrr reverse recovery charge
-Coss output capacitance
-Eoss/Qoss
-Vsd forward voltage drop
-Qg gate charge

Chapter 4: Gate driving guidelines

Chapter 5: Benchmarking in target applications
-3kW LLC converter

Although the example application is an LLC converter, the base basics apply to the phase shift topology regarding the soft-switching of the power switches.

Best regards,
Pablo

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1 Reply
Pablo_EG
Moderator
Moderator
Moderator
First question asked 250 sign-ins 250 replies posted

Hello Harsh,

Thank you for posting on Infineon Community.

Q: Can 650V SiC Mosfet operate at 1.2MHz switching frequency?
A: Yes, it can be done.

Q: Any considerations while operating at such frequency?
A:

Qoss discharging
As it is a soft-switched topology, Qoss needs to be discharged to make sure the body diode turns on and soft switching happens.
The main drawback of SiC technology is the high body diode voltage drop, Vf. While for Si it is only about 1V, SiC's is 3.6V.
This means that the periods when the body diode is conducting should be minimized, for efficiency's sake.
Tdon, Tdoff, Tr, and Tf impact the deadtime that needs to be implemented.
When operating at high switching frequencies, the deadtime becomes more significant, as it takes a larger portion of the switching cycle.

dV/dT
Due to the need to charge the Coss, at startup and low loads, there is a risk of hard commutation.
Ensure that the gate driver is as close to the switches as possible to minimize the gate loop, as the high dV/dt could trigger unintended turn-on due to crosstalk.
SiC's output capacitance is more linear than Si, which allows for faster switching times with less overshoot.
However, make sure that the parasitic inductance of the power loop is minimized.
If a hard-switching event happens, the high dV/dt could induce a voltage spike which in extreme cases could go over the Vds_max parameter and make the switch go into avalanche.

Gate driving
SiC has different gate requirements than Si.
Unlike Si devices, SiC does not saturate at 20 Vgs, therefore an 18V Vgs is recommended for the lowest possible Rdson.
Due to the best-in-class Crss/Ciss ratio, the 650V CoolSiC devices can be turned off at 0V with minimal gate voltage spiking.
Keeping Vgs_min at 0V also has the added benefits of lower Vgh_th drift in time, which prevents the deterioration of the device.
If negative undershoots are a problem, a clamping diode can be used between the gate and source (or kelvin source) of the switch.

For further information on the CoolSiC technology and its utilization in soft-switching topologies, please refer to the following application note:

https://www.infineon.com/dgdl/Infineon-MOSFET_CoolSiC_650V_SiC_trench_power-ApplicationNotes-v02_00-...

Here, the following topics are discussed in detail, which could be relevant to your application.

Chapter 3: technology parameters
-Qrr reverse recovery charge
-Coss output capacitance
-Eoss/Qoss
-Vsd forward voltage drop
-Qg gate charge

Chapter 4: Gate driving guidelines

Chapter 5: Benchmarking in target applications
-3kW LLC converter

Although the example application is an LLC converter, the base basics apply to the phase shift topology regarding the soft-switching of the power switches.

Best regards,
Pablo