How to Eliminate Voltage Spikes of Inverter Output Waveform

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wohehe123
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The output waveform of my inverter is like this (yellow curve):

wohehe123_2-1675589068388.png

I assume this has something to do with the DC bus, for I didn't add any bus capacitance. After adding one 220uF electrolytic capacitor and one 100nF capacitor, the waveform became like this:

wohehe123_3-1675589256236.jpeg

It seems to be better, but the voltage spike is still large. I wonder if this phenomenon is normal ? If not, what can I do to improve the output waveform of my inverter. I tried to increase the gate resistor from 5.1Ohms to 50Ohms, but it would't help to better the waveform and only to decrease the switching speed.

PS: the gate driver schematic diagrams is presented as below.

wohehe123_4-1675589848162.pngwohehe123_5-1675589911392.png

 

 

 

 

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Jingwei
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The snubber, dc link capa, clamp diode at output are the best ways to do now since you cant redesign your PCB.

As for parasitic Inductance reduction. I would like to take action at 3 points.

1. Minimize power loop. Means you need to short PCB trace of your power loop. And using copper area to reduce EsL and ESR.

2. Minimize driver loop. Same. Make sure all the driver comp very near to each other, use LARGER trace.

3. Keep the power circle small, which will help the reduction of Parasitic inductance generated by high frequency of current flow.

 

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Jingwei
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Hi,

Basic guess is the gate loop design. The parasitic inductance of gate loop is too high. Or the parasitic inductance Ls, which is from source of mosfet to ground. You can upload your board design to check out where is the main problem. Anyway the spike is mostly caused by the parasitic parameter.

Below are some steps to do without changing pcb trace.

  1. Snubber Circuits: A snubber circuit is a passive network that is placed across the switching device (such as a MOSFET or IGBT) to reduce the voltage transients that occur during the switch transition. A snubber circuit typically consists of a capacitor and a resistor.

  2. LC Filter: An LC filter can be used to smooth out the inverter's output waveform by providing a low-pass filter effect. The LC filter is made up of an inductor and a capacitor, and it is placed between the inverter and the load.

  3. PWM Control: By adjusting the PWM (pulse width modulation) parameters, you can reduce the voltage spikes in the output waveform. For example, reducing the frequency or duty cycle of the PWM signal can help to reduce the voltage spikes.

  4. DC Link Capacitor: By increasing the size of the DC link capacitor, you can provide more energy storage and help to reduce the voltage spikes in the output waveform.

  5. Output Voltage Feedback: By using a feedback loop to control the output voltage, you can improve the stability of the inverter and reduce the voltage spikes. For example, you might use a voltage feedback control loop to regulate the output voltage to a desired value.

  6. Add clamp diode to filter the spike, you can search in IEEE, there are some good article talking about it.

Steven

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wohehe123
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Thank you Jingwei! Your answer is comprehensive and insightful. Out of my curiosity, could you please show me how to reduce the side effect of parasitic inductance taking my PCB for example,  thank you so much.

 

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Jingwei
Moderator
Moderator
Moderator
250 sign-ins 10 likes given 100 solutions authored

The snubber, dc link capa, clamp diode at output are the best ways to do now since you cant redesign your PCB.

As for parasitic Inductance reduction. I would like to take action at 3 points.

1. Minimize power loop. Means you need to short PCB trace of your power loop. And using copper area to reduce EsL and ESR.

2. Minimize driver loop. Same. Make sure all the driver comp very near to each other, use LARGER trace.

3. Keep the power circle small, which will help the reduction of Parasitic inductance generated by high frequency of current flow.

 

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