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WEN-YUNG
Level 3
Level 3
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Dear IFXer,

Why the Miller Plateau of SiC MOSFET have different level when MOSFETs turn on/off?

below is IMZA120R40M1H used in low speed leg fo TTPL 

WENYUNG_0-1702951465223.jpeg

 

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1 Solution
AZIZ_HASSAN
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Hello,

Thank you  for your reply. Below are my comments for your query.

1) There are broadly two reasons for miller plateau level difference during turn off and on. One is because of voltage across the device i.e. Vds for SiC . The miller or transfer capacitance is non- liner and in direct proportional to Vds. So, during turn on, when the vgs rises from vth to miller region, the Vds is same during this period  as it was during the turn off (full voltage across drain and source ) and during turn off, when the vgs falls from full value(15V in your case) to miller plateau, during this region, the Vds already start to rise but do not reach to full value. and hence since there is Vds voltage difference during these two scenario, the miller capacitance which is non- linear will behave differently and hence resulting into different miller voltage level.

Another reason is different gate resistance. If you use different gate resistance for turn on and off, the gate current will be different and hence the charging and discharging of non- linear capacitance will be different resulting into different miller level.

2) Regarding your query about MOSFET current turn off, can you please share the waveform to analyze once.

Thanks,

AZIZ

 

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AZIZ_HASSAN
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50 likes received 5 likes given 250 sign-ins

Hello,

Yes you observation is correct that miller will be at different voltage levels during turn on and off. However, since the waveform is not good, I request you provide the below details to help you.

1) What is the application and what driver IC you are using?

2) Are you using different on and off gate resistance?

3) What is the turn on and turn off gate voltage ?

Thanks,

AZIZ

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Dear AZIZ,

I am feedback as below and my further question MOSFET’s current turn off after or before the miller plateau? and what the reason affected the miller plateau level when SiC MOSFET turn off?

1. It is OBC design, the Input voltage come form 220VAC and output 800VDC, the gate driver IC is Si8233, 120R40M1H was used in Low speed leg for totem pole PFC rectifier.

2. The turn on/off Rg are different.

3. The turn on/off voltage are 15V and -2V, respectively.

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AZIZ_HASSAN
Moderator
Moderator
Moderator
50 likes received 5 likes given 250 sign-ins

Hello,

Thank you  for your reply. Below are my comments for your query.

1) There are broadly two reasons for miller plateau level difference during turn off and on. One is because of voltage across the device i.e. Vds for SiC . The miller or transfer capacitance is non- liner and in direct proportional to Vds. So, during turn on, when the vgs rises from vth to miller region, the Vds is same during this period  as it was during the turn off (full voltage across drain and source ) and during turn off, when the vgs falls from full value(15V in your case) to miller plateau, during this region, the Vds already start to rise but do not reach to full value. and hence since there is Vds voltage difference during these two scenario, the miller capacitance which is non- linear will behave differently and hence resulting into different miller voltage level.

Another reason is different gate resistance. If you use different gate resistance for turn on and off, the gate current will be different and hence the charging and discharging of non- linear capacitance will be different resulting into different miller level.

2) Regarding your query about MOSFET current turn off, can you please share the waveform to analyze once.

Thanks,

AZIZ

 

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Dear AZIZ,

Thank you very much! It is clear explanation for me and I'll try to measure the Id current for you.

before that, 1) looks the plateau level(Vp) lower than threshold level(Vth), Right? 2) In this situation, just make sure the Vgs low than Vth, the MOSFET will turn off when the Vgs falls from full value(15V) to plateau till low Vth, right?

Regards,

KUO

 

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AZIZ_HASSAN
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50 likes received 5 likes given 250 sign-ins

Hello,

This not possible that the miller plateau is lower than Vth. As I told in earlier comment, the waveform is not good.  Please try to capture better waveform then we can comment on that.

Thanks,

AZIZ

 

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