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如何減少SiC MOSFET開關時由於di/dt導致較大電壓尖峰?有沒有具體方案或案例參考?

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/%E5%A6%82%E4%BD%95%E5%87%8F%E5%B0%8FSiC-MOSFET%E5%BC%80%E5%85%B3%E6%97%B6DS%E6%9E%81%E7%94%B5%E5%8E%8B%E5%B0%96%E5%B3%B0/td-p/732292

1 解決方案
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Hello @Stone-Mao ,
If provided answer resolves your query then, we request you to click on accept as a solution.
譯文:如果所提供的答案解決了您的問題,請點擊接受作為解決方案。

Thank you,
Vicky S

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/%E5%A6%82%E4%BD%95%E5%87%8F%E5%B0%8FSiC-MOSFET%E5%BC%80%E5%85%B3%E6%97%B6DS%E6%9E%81%E7%94%B5%E5%8E%8B%E5%B0%96%E5%B3%B0/m-p/732564

在原始文章中檢視解決方案

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3 回應
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非常感謝!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/%E5%A6%82%E4%BD%95%E5%87%8F%E5%B0%8FSiC-MOSFET%E5%BC%80%E5%85%B3%E6%97%B6DS%E6%9E%81%E7%94%B5%E5%8E%8B%E5%B0%96%E5%B3%B0/m-p/732536

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Hello,
1. CoolSiC ™ Mosfet provides good control of switching transients by the gate resistor value. By increasing the gate resistance di/dt and dv/dt of the device can be reduced which mitigates the spikes and ringing. However, the penalty is of increased switching loss.

2. Improving the layout : By optimizing the power path of the circuit, parasitic inductance of the path can be reduced and thus spikes and ringing.

譯文:
1.CoolSiC ™ Mosfets 可透過閘極電阻值對開關瞬態進行優異的控制。透過增加閘極電阻,可以降低裝置的di/dt 和dv/dt 值,從而減少尖峰和振鈴。然而,這樣做的代價是增加開關損耗:透過優化電路的電源路徑,可以降低路徑的寄生電感,從而減少尖峰和振鈴

CoolSiC ™ 1200 V SiC MOSFET Application Note請參閱更多詳情;

Best regards,
Vicky S

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/%E5%A6%82%E4%BD%95%E5%87%8F%E5%B0%8FSiC-MOSFET%E5%BC%80%E5%85%B3%E6%97%B6DS%E6%9E%81%E7%94%B5%E5%8E%8B%E5%B0%96%E5%B3%B0/m-p/732529

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Hello @Stone-Mao ,
If provided answer resolves your query then, we request you to click on accept as a solution.
譯文:如果所提供的答案解決了您的問題,請點擊接受作為解決方案。

Thank you,
Vicky S

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOSFET-Si-SiC/%E5%A6%82%E4%BD%95%E5%87%8F%E5%B0%8FSiC-MOSFET%E5%BC%80%E5%85%B3%E6%97%B6DS%E6%9E%81%E7%94%B5%E5%8E%8B%E5%B0%96%E5%B3%B0/m-p/732564

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