Legacy microcontrollers Forum Discussions

Hi, there

I was trying to trying to put the mcu to a low-power standby mode. Here is the pseudo codes:

while (1)

{

     if(low_power_mode)

     {

          SCB->SCR |= 0x04;     // Enable Deep Sleep Mode

          FM_DS->PMD_CTL = 0x00;     // Standby Stop Mode

          FM_CRG->STB_CTL |= 0x1ACC0006;     // Deep Standby Mode

          FM_DS->RCK_CTL &= 0x02;     // stop supplying Clock to RTC macro

          FM_DS->DSRAMR = 0x03;     // SRAM retention enable.

          FM_CRG->CSV_CTL &= 0xFFFC;    // Clear Sub-Clock Supervisor Reset and interrupt.

          __disable_irq();

          __WFI();

     }

}

I use MDK as my development environment and the PDL version is 2.1.

[Device]

MB9BF568RPMC

[Backgrounds]

- Hardware transfer is performed by DSTC.

- Selecting "transfer mode1".

A "DES open error" has occurred during DSTC transfer.

-> I have confirmed that the value of EST[2:0] in the MONERS register is "101".

We confirmed the DES open error occurrence conditions described in “DES Open Error” on page 527 of “32-Bit Microcontroller FM4 Family Peripheral Manual”.

However, the values of DES0 and DES1 do not meet any of the following conditions.

================================================================

- DV[1:0]==00

- PCHK[3:0] != (DES0[27:24] ^ DES0[23:20] ^ DES0[19:16] ^ DES0[15:12] ^ DES0[11:8] ^ DES0[7:4])

- One of the two bits of the reserved area of DES0 is 1.

- TW[1:0]==11

- CHRS[5:4]==11

- (CHRS[5]==0) &&(CHRS[3]==0)&&(CHRS[1]==0) &&(CHLK ==1)

- (MODE==1)&&(IIN!=0x00)&&(IRM==0x00)

- (MODE==1)&&(IIN!=0x00)&&(IRM>IIN)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (ORM != 0x0001)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0) && (IRM != 0x01)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (IIN != 0x01)

- (DV[1]==1)&&(SAC[0]==0)&&(ORL[1]==0)

- (DV[1]==1)&&(DAC[0]==0)&&(ORL[2]==0)

================================================================

Q1.

Are there any other conditions that cause a “DES open error” other than the above values for DES0 and DES1?

Q2.

The DSTC HW transfer uses 3channels.

The frequency of DES open errors increased when three input edge detection interrupts occurred simultaneously.

Is there a case where the arbitration operation does not function normally?

If so, would you tell me the workaround if there is one?

*I am referring to “3.2.5 Arbitration of Transfer Requests” on page 524 of “32-Bit Microcontroller FM4 Family Peripheral Manual”.

Best Regards,

Harukawa

--- 以下、日本語 ---

■デバイス

MB9BF568RPMC

■問合せ内容

*背景

・DSTCでhardware転送を行っています。(3チャネルを使用しています)

・転送モード1を選択しています

DSTC転送中に「DESオープンエラー」が発生しています。

-> MONERSレジスタのEST[2:0]の値が"101"になっていることを確認しています。

「32-Bit Microcontroller FM4 Family Peripheral Manual」のP527の「DES Open Error」に記載されているDESオープンエラー発生条件を確認しました。

しかし、DES0とDES1の値は下記の条件のいずれにも合致していません。

================================================================

- DV[1:0]==00

- PCHK[3:0] != (DES0[27:24] ^ DES0[23:20] ^ DES0[19:16] ^ DES0[15:12] ^ DES0[11:8] ^ DES0[7:4])

- One of the two bits of the reserved area of DES0 is 1.

- TW[1:0]==11

- CHRS[5:4]==11

- (CHRS[5]==0) &&(CHRS[3]==0)&&(CHRS[1]==0) &&(CHLK ==1)

- (MODE==1)&&(IIN!=0x00)&&(IRM==0x00)

- (MODE==1)&&(IIN!=0x00)&&(IRM>IIN)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (ORM != 0x0001)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0) && (IRM != 0x01)

- (MODE==1)&&(DV[1]==1)&&(ORL[0]==0)&& (IIN != 0x01)

- (DV[1]==1)&&(SAC[0]==0)&&(ORL[1]==0)

- (DV[1]==1)&&(DAC[0]==0)&&(ORL[2]==0)

================================================================

Q1.

DES0,DES1の上記の値以外に「DESオープンエラー」が発生する条件はあるのでしょうか。

Q2.

DSTCのHW転送では3チャネルを使用しています。

入力エッジ検出割込みが3つ同時に起きると、DESオープンエラーの発生頻度が上がりました。

調停動作が正常機能しない事例があるのでしょうか。

もしあるならその回避策を教えてくれませんか。

*「32-Bit Microcontroller FM4 Family Peripheral Manual」のP524の「3.2.5 Arbitration of Transfer Requests」を参照しています。

  Please give me below Device's Fab and ASSEMBLY site

CY91F525KSDPMC1-GSE2

CY96F313ASBPMC-GS-UJE2

CY96F353ASBPMC1-GS-UJE2

CY96F646RBPMC-GS-UJE2

CY96F625RBPMC1-GS119UJE2

CY96F625RBPMC1-GS121UJE2

CY96F673ABPMC1-GS103UJE2

Dear all,

For PTN194501,  MB9BF566RPMC-G-JNE2 is migrated to CY9BF566RPMC-G-MNE2.

Is there any change in function, specification or form?

Also please let me know if there is any change in fab, assembly and test site?

Thank you,Shun Furusawa