Legacy microcontrollers Forum Discussions
hi there,
I currently working on FR81s MCU MB91524FS with SOFTune Compiler V65L06R01 for FBL project and I have 2 issue with compiler generated code in FBL running environment, that is, no Flash code access during Flash operation.
1, the switch-case code generation:
it looks to me that the compiler generated a 'branch_table' for some switch-case C code. here is the example:
FR Family SOFTUNE Assembler V60L09 2021-05-24 10:30:46 Page: 70
- SOURCE LISTING - ( fbl_cw )
SN LOC OBJ LLINE SOURCE
RA 00000814 9F8D00000000 R 2832 LDI:32 #L_50415,R13
RA 0000081A B420 2833 LSL #2,R0
RA 0000081C 0000 2834 LD @(R0,R13),R0
2835 ;-------table_branch
RA 0000081E 9700 2836 JMP @R0
2837
CO 00000018 -----------<CONST>----------- 2838 .section CONST, CONST, ali
gn=4
CO 00000018 - 00000018 [0] < [4] 2839 .align 4
CO 00000018 2840 L_50415:
2841 ;-------begin_of_branch_table
CO 00000018 00000000R 2842 .word L_293
CO 0000001C 00000000R 2843 .word L_288
CO 00000020 00000000R 2844 .word L_290
CO 00000024 00000000R 2845 .word L_293
CO 00000028 00000000R 2846 .word L_293
CO 0000002C 00000000R 2847 .word L_291
2848 ;-------end_of_branch_table
2849
RA 00000820 ----------<RAMCODE>---------- 2850 .section RAMCODE, CODE, al
ign=2
RA 00000820 - 00000820 [0] < [2] 2851 .align 2
because this table is CONST section located in Flash, while the function contains this switch-case code shall be relocated to RAM (RAMCODE) for Flash operation, that would cause MCU hung. my question is is there any way to prevent compiler to generate so call branch table?
2, the 2nd question is about Intrinsic function
the C division '/' would involve compiler intrinsic function from Lib911, i could see that function like ' __divxx' was allocated in Flash, so as the first scarino, in FBL when Flash is not accessible for read, a division code would result in MCU hung.
i notice that in https://community.cypress.com/t5/Knowledge-Base-Articles/Optimization-Level-of-SOFTUNE-C-Compiler-in-FR-Family-FR81S-MCUs/ta-p/253528 it mentioned in Optimization Level 4, inline expansion is implemented, but unfortunately, i may not be able to apply any optimization option for this project.
Thanks in advance,
Walker
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Is there information on recommended land patterns for this device?
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https://www.cypress.com/file/126296/download
Thank you,
Tetsuo
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We have the following wishes:
- automotive classification
- the life of not less than 10 years,
- number of legs from 48 (for the youngest in the line) to ~ 200 (for the oldest in the line),
- LQFP package, - power supply (preferably + 5V),
- availability of CAN, for the younger (48 pin) 1 piece min, but preferably 2 pieces, for all the others at least 2 pieces, in the older 4 pieces,
- presence of FPU,
- ADC: at least 12 bit, for older 2 modules and up to a total of 40 channels,
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- ROM memory: low-end models 256kbytes, high-end models 2048kbytes,
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- availability of a free compiler.
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I use a CY96F315RS with a 16Mhz Resonator on 48Mhz (Murata CSTCE) in an application with Stop Mode for standby.
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Regards,
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Hello, where can I download them?
Regards,
Jackson
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