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OliverG
Level 1
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Level 1

Hello.

I implemented from [1] the chapter 8.14.3.1 "ECC Software Testing Support". I implemented the chapter for the DSRAM, DPRAM, and PSRAM.
[1] chapter 8.14.3.1 also states "If ECC operation is enabled (ECCCON.xEN = 1) the corrected data value (2000H) is read and an ECC error is indicated.".
Above second underlined is working for DSRAM, DPRAM, and PSRAM. That’s fine. And no question.
Above first underlined is working for DSRAM and DPRAM. That’s fine. And no question.
Above first underlined is not working for PSRAM. This is my problem.

I allow to describe my problem a little bit more detailed, with parts of my implementation. For the relevant code parts of my implementation see [2].


At [2] line 31 "POINT 1" is observed:

  • errorcode has the value FCT_NO_ERROR.
  • biosRamEccParityTestRegECCSTAT has the value 2.

At [2] line 38 "POINT 2" is observed:

  • errorcode has the value FCT_NO_ERROR.
  • biosRamEccParityTestRegECCSTAT has the value 1.

At [2] line 45 "POINT 3" is observed:

  • errorcode has the value FCT_ERROR_ARGUMENT; reason: [2] line 80 "POINT 4" is executed. Note:
    • For [2] line 82 stated "xxxLocation6" were following different values observed: 0, 0xC0FA, or 4.
  • biosRamEccParityTestRegECCSTAT has the value 4.

So my above stated problem boils down to my following question: Why is for the PSRAM, at [2] line 64 "POINT 5", [1] chapter 8.14.3.1 stated "If ECC operation is enabled (ECCCON.xEN = 1) the corrected data value (2000H) is read" not fulfilled?

References:
[1] https://www.infineon.com/dgdl/xe166h_um_v1.1_2009_04.pdf?fileId=db3a304328c6bd5c01291210b0cb099d
[2] Attached Ecc.pdf

Regards
Oliver.

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OliverG
Level 1
10 sign-ins First question asked 5 sign-ins
Level 1

Dear Infineon team.

May I ask you for the current status of my above question?

Regards
Oliver.

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