Hello.
[1] chapter 8.14.3.1 states "The ECC error detection can be triggered on purpose to test the detection itself and the associated trap routine. This test option is available for RAMs". So, previous stated chapter describes how the RAM ECC error detection can be tested. That’s fine.
My question: How can the flash ECC error detection be tested?
Question reason: In [1] chapter 3.10.7.1 I see the flash ECC description. But I don’t find in [1] a chapter for the flash, which is similar to (above stated) [1] chapter 8.14.3.1.
Regards
Oliver.
References:
[1] https://www.infineon.com/dgdl/xe166h_um_v1.1_2009_04.pdf?fileId=db3a304328c6bd5c01291210b0cb099d
