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JuIn_1625121
Level 5
Level 5
100 sign-ins First solution authored 100 replies posted

The customer connects reset port of MB95F563H and reset IC, and these are pulled-up.

The reset IC'S port is Open drain.

And, the IC start output hi-impedance when Vcc rises up 2.5V.

The customer thinks reset port voltage start to rise quickly when Vcc rises up 2.5V.

However, in the measurement result, the port voltage starts to rise with a delay of 1 ms.

measured illust.png

I think the behavior caused by Power On Reset.

Is it correct?

If No, please tell me why.

Best Regards,

Inoue

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1 Solution
JuIn_1625121
Level 5
Level 5
100 sign-ins First solution authored 100 replies posted

Hi Yoshioka-san,

Your document is for MB95630H series.

So, I checked this document.

http://www.cypress.com/documentation/technical-reference-manuals/mb95560h570h580h-series-8-bit-micro...

I found `CR Clock Oscillation Stabilization Wait Time` at page 66.

The stabilization wait time that I calculated is 1.23ms.

I think this result and outputing power-on-reset are considered to be the cause of the period of L at RST line in customer's waveform.

Thank you.

Best Regards,

Inoue

View solution in original post

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14 Replies
ChaoHaiM_11
Employee
Employee
5 sign-ins First question asked 10 solutions authored

Hello Inoue,

pastedImage_1.png

FYI, the release delay time(Tond) is needed when power on.

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Hi chma,

Thank you for your help.

If Tond is about 1ms and reset port outputs Low during Power On Reset,

I think the customer's measure result(simple figure in my first question) is explained by them.

So, I want to know how long is Tond and what is behavior of reset port during Power On Reset.

Best Regards,

Inoue

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Anonymous
Not applicable

I think this issue depends on the reset IC.

Please retry without the reset IC.

Best Regards,

Toshifumi Yoshioka

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Anonymous
Not applicable

There is also a "Reset output enable/disable bit" setting.

Please refer the hardware manual (page 394)

http://www.cypress.com/documentation/technical-reference-manuals/mb95560h570h580h-series-8-bit-micro...

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Hi Yoshioka-san,,

Thank you for your answer.

I confirmed it and told the customer.

Best Regards,

Inoue

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Hi Yoshioka-san,

The customer has two additional question.

1)When "Reset output enable/disable bit" is set enable, Is the behavior(the port outputs low for 1ms) as per the specification?.

   If yes, are there any evidence(document, etc...)?

2)The customer connects the port to reset IC's port that is Open drain.

    If "Reset output enable/disable bit" is set enable, is there any problem?

    (I think there is no problem, because it will be like wired OR.)

Best Regards,

Inoue

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Hi Yoshioka-san,

The customer gave additional information just now.

a) Reset output enable/disable bit was set Disable. 

    The waveform attached the first question is with Reset output disable.

b) Without ResetIC, similar waveform (1ms delay from Vcc rising to reset rising) is measured.

What cause the delay?

Please tell as soon as possible, because the customer is very hurry.

If information is not enough, please tell what you need.

Best Regards,

Inoue

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Anonymous
Not applicable

How do the reset IC operate when not connecting MCU?

Best Regards,

Yoshioka

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The reset IC is S-80825CNNB-B8KT2G.

Please check the following documents.

https://www.ablic.com/en/doc/datasheet/voltage_detector/S808xxC_E.pdf

Without ResetIC, similar waveform (1ms delay from Vcc rising to reset rising) is measured.

So, I think it does not matter how do the reset IC operate when not connecting MCU.

Best Regards,

Inoue

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Anonymous
Not applicable

This is my imagination, is there a capacitor on the reset IC's output?

If it exist, please remove and re-mesure.

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Anonymous
Not applicable

There is described following information in the datasheet page 25

.http://www.cypress.com/documentation/datasheets/cy95560h-series-cy95570h-series-cy95580h-series-new-...

• Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode

It depends on external oscillator but I think that 1ms is stabilization wait time.

When the problem is resolved. Could you please click "Correct Answer".

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JuIn_1625121
Level 5
Level 5
100 sign-ins First solution authored 100 replies posted

Hi Yoshioka-san,

The customer uses internal CR oscillator(4MHz).

In that case, is 1ms stabilization wait time?

If yes, please tell where is described it.

Capacitor is for noise control.

I remove the capacitor and reset IC, and measured.

WithoutC5andIC2.JPG

1)Vcc

2)RST

There is about 0.8ms delay.

Best Regards,

Inoue/Hakuto

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JuIn_1625121
Level 5
Level 5
100 sign-ins First solution authored 100 replies posted

Hi Yoshioka-san,

Your document is for MB95630H series.

So, I checked this document.

http://www.cypress.com/documentation/technical-reference-manuals/mb95560h570h580h-series-8-bit-micro...

I found `CR Clock Oscillation Stabilization Wait Time` at page 66.

The stabilization wait time that I calculated is 1.23ms.

I think this result and outputing power-on-reset are considered to be the cause of the period of L at RST line in customer's waveform.

Thank you.

Best Regards,

Inoue

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