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Using the CY7C2565XV18 verilog model along with the tb file to simulate on vivado, it was found that the read data was delayed by 3 beats of the clock not the given 2.5 beats

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/SRAM/%E4%BD%BF%E7%94%A8CY7C2565XV18-verilog%E6%A8%A1%E5%9E%8B%E4%BB%A5%E5%8F%8Atb%E6%96%87%E4%BB%B6%E5%9C%A8vivado%E4%B8%8A%E4%BB%BF%E7%9C%9F-%E5%8F%91%E7%8E%B0%E8%AF%BB%E6%95%B0%E6%8D%AE%E5%BB%B6%E8%BF%9F%E4%BA%863%E6%8B%8D%E6%97%B6%E9%92%9F%E4%B8%8D%E6%98%AF%E7%BB%99%E5%AE%9A%E7%9A%842-5%E6%8B%8D/td-p/739017

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Translation_Bot
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Hi xiaopeng1988,

How do you define a 3 beat delay? Take a look at the waveforms in our datasheet for 2.5 clock latency and compare them with yours:

Janine_Y_0-1713163417774.png

https://www.infineon.com/dgdl/Infineon-CY7C2563XV18_CY7C2565XV18_72-Mbit_QDR(R)_II+_Xtreme_SRAM_Four...

Best Regards.

Janine

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/SRAM/%E4%BD%BF%E7%94%A8CY7C2565XV18-verilog%E6%A8%A1%E5%9E%8B%E4%BB%A5%E5%8F%8Atb%E6%96%87%E4%BB%B6%E5%9C%A8vivado%E4%B8%8A%E4%BB%BF%E7%9C%9F-%E5%8F%91%E7%8E%B0%E8%AF%BB%E6%95%B0%E6%8D%AE%E5%BB%B6%E8%BF%9F%E4%BA%863%E6%8B%8D%E6%97%B6%E9%92%9F%E4%B8%8D%E6%98%AF%E7%BB%99%E5%AE%9A%E7%9A%842-5%E6%8B%8D/m-p/739179

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Translation_Bot
Community Manager
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100 likes received

Hi xiaopeng1988,

How do you define a 3 beat delay? Take a look at the waveforms in our datasheet for 2.5 clock latency and compare them with yours:

Janine_Y_0-1713163417774.png

https://www.infineon.com/dgdl/Infineon-CY7C2563XV18_CY7C2565XV18_72-Mbit_QDR(R)_II+_Xtreme_SRAM_Four...

Best Regards.

Janine

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/SRAM/%E4%BD%BF%E7%94%A8CY7C2565XV18-verilog%E6%A8%A1%E5%9E%8B%E4%BB%A5%E5%8F%8Atb%E6%96%87%E4%BB%B6%E5%9C%A8vivado%E4%B8%8A%E4%BB%BF%E7%9C%9F-%E5%8F%91%E7%8E%B0%E8%AF%BB%E6%95%B0%E6%8D%AE%E5%BB%B6%E8%BF%9F%E4%BA%863%E6%8B%8D%E6%97%B6%E9%92%9F%E4%B8%8D%E6%98%AF%E7%BB%99%E5%AE%9A%E7%9A%842-5%E6%8B%8D/m-p/739179

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