How does stablization wait time work in PDL

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XiaoPing_Yang
Level 4
Level 4
25 replies posted 10 replies posted 10 questions asked

Hi Sir,

     Now I have a question when I set the  stablization wait time  of  main clock. In the FM3_Peripheral_Manual_Main_Part_TRM, on page 53 "Access the Clock Satbilization Wait Time Register(CSW_TMR). Set the main clock oscillation stablization wait time.".But I check the code in pdL ,  as follows:

    FM_CRG->SCM_CTL_f.MOSCE = 1u;

    if(TRUE == bBlock)

    {

       while(1u != FM_CRG->SCM_STR_f.MORDY);

    }

   I think there is no use of  "Access the Clock Satbilization Wait Time Register(CSW_TMR). Set the main clock oscillation stablization wait time."

   Is that right?

   Thanks.

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1 Solution

The wait time settings will be written to each clock stabilization wait time register in the Clk_Init() function.

Each the setting become effective after enabling each clock.

In the Clk_EnableMainClock() function, the PDL sets MOSCE bit in SCM_CTL register to enable MainClock.

Then, the device will wait for a period specified in the Main clock stabilization wait time register.

The MORDY bit in the SCM_STR register will be set after internal counter reached to the specified period.

Roy Liu

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3 Replies
Roy_Liu
Moderator
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5 comments on KBA First comment on KBA 10 questions asked

Hi Xiaoping,

Which version of PDL you are looking at, and from which file you find that code snippet?

Thanks

Roy

Roy Liu
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Hi Roy,

     PDL 2.02 .

     The fie is clk.c.

     Thanks.

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The wait time settings will be written to each clock stabilization wait time register in the Clk_Init() function.

Each the setting become effective after enabling each clock.

In the Clk_EnableMainClock() function, the PDL sets MOSCE bit in SCM_CTL register to enable MainClock.

Then, the device will wait for a period specified in the Main clock stabilization wait time register.

The MORDY bit in the SCM_STR register will be set after internal counter reached to the specified period.

Roy Liu