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shma_1538871
Level 4
Level 4
25 replies posted 25 sign-ins 10 replies posted

Hi All

I have a question about baud rate calculation of FM4.

Peripheral manual mentions sampling timing margin.

Margin of minimum data rate is 1 clock.

Margin of maximum data rate is 2 clock.

I'd like to know the reason why margin is not same.

Please tell me the detail of 1 clock and 2 clock margin.

Best regards

Matsushita

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GeonaP_26
Moderator
Moderator
Moderator
250 solutions authored 100 solutions authored 50 solutions authored

Hello Matsushita-San,

One or two bus clock cycles in the fomula of FLmin/FLmax are additional bus clock cycles required by MFS circuit to sample the inputs.

The theoretical FLmin and FLmax formula is,

FLmin=(11bits * (V+1) – (V+1)/2 + 1)/φ

FLmax=(21/20 * 11 * (V+1))/φ

However, practically MFS requires one or two additional bus clock cycles to sample the inputs.  Thus, practical formula for FLmin and FLmax is;

With the sampling timing margin of one bus clock (φ), FLmin = (11bits × (V+1) - (V+1)/2 + 2)/φ

With the sampling timing margin (φ) of two bus clocks (φ), FLmax=(21/20 * 11 * (V+1) - 44/20)/φ

Best Regards,

Geona Mary

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GeonaP_26
Moderator
Moderator
Moderator
250 solutions authored 100 solutions authored 50 solutions authored

Hello Matsushita-San,

One or two bus clock cycles in the fomula of FLmin/FLmax are additional bus clock cycles required by MFS circuit to sample the inputs.

The theoretical FLmin and FLmax formula is,

FLmin=(11bits * (V+1) – (V+1)/2 + 1)/φ

FLmax=(21/20 * 11 * (V+1))/φ

However, practically MFS requires one or two additional bus clock cycles to sample the inputs.  Thus, practical formula for FLmin and FLmax is;

With the sampling timing margin of one bus clock (φ), FLmin = (11bits × (V+1) - (V+1)/2 + 2)/φ

With the sampling timing margin (φ) of two bus clocks (φ), FLmax=(21/20 * 11 * (V+1) - 44/20)/φ

Best Regards,

Geona Mary

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