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Legacy microcontrollers Forum Discussions

Anonymous
Not applicable

Hello, I have a question for Traveo s6j3200 MCU. It is related to ECC error detection of TCFLASH memory, when access to memory is through ATCM port. I'd like to disable generating of abort on single bit errors, but to have the automatic error correction operating (SEC-DED enabled).

Is this behaviour achieved by setting the following configuration:

ACTLR.ATCMECEN=0

ACTLR.ATCMPCEN=1

?

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HongyanW_86
Moderator
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100 solutions authored 100 replies posted 50 solutions authored

Hello,

No, ATCMPCEN is used to disable or enable ECC check.

To enable correction of ATCM single-bit ECC error, you need to configure ATCMECC to 0 (reset value). In this way, you will not get ABORT for single-bit ECC error of TCFLash (via ATCM).

//Secondary Auxiliary Control Register

bit 2

ATCMECC

Correction for internal ECC logic on ATCM port.[d]

0 = Enabled. This is the reset value.

1 = Disabled.

For more information, please kindly refer to ARM Cortex R5 TRM. ARM Information Center

Best regards,

Amy Wang

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HongyanW_86
Moderator
Moderator
Moderator
100 solutions authored 100 replies posted 50 solutions authored

Hello,

No, ATCMPCEN is used to disable or enable ECC check.

To enable correction of ATCM single-bit ECC error, you need to configure ATCMECC to 0 (reset value). In this way, you will not get ABORT for single-bit ECC error of TCFLash (via ATCM).

//Secondary Auxiliary Control Register

bit 2

ATCMECC

Correction for internal ECC logic on ATCM port.[d]

0 = Enabled. This is the reset value.

1 = Disabled.

For more information, please kindly refer to ARM Cortex R5 TRM. ARM Information Center

Best regards,

Amy Wang

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