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cross mob
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Hello Infineon

We are currently working on TC38x controller. Here I would like to know the definition and use case of multiple memories(DSPR, PSPR, dLMU & LMU) which are defined in the controller architecture. Could you please provide the in detailed details of those memories.

Regards,
Narendra
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cwunder
Employee
Employee
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These memories are described in the user's manual with their respective access times.

In the TC3xx devices the DSPR, PSPR, and dLMU are located next to each CPU. The DSPR offers the fastest access time for data to its core, the PSPR offers the fastest access time to the program side of the core (Harvard architecture). Whereas the dLMU should be primarily used for the respective core but also shared with other cores. The LMU can be shared with all cores.
User22771
Level 1
Level 1
Hi,

here is another question regarding DLMU and LMU: in TC365 they have different address and from the user's point of view they are two different phyiscal units, but in the practice the contents are tied to each other, modifiying hex value in one part the other becomes the same. Is DLUM not a mapping of LMU or vice versa?
My problem is when user want to run some simple RAM Test manually ( fill the DLMU/LMU with test pattern and read out , compare, please don't ask why such "wondering" tests) should he check the both or only one of them?

Best Regards
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cwunder
Employee
Employee
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On TC3x devices a generic term of Local Memory Memory (LMU) can be further classified into two categories, global LMU and distributed LMU (dLMU). The DLMU's and LMU's are separate memories that also have different access times depending on what master is accessing it. You can also access it via cached or non-cached addresses.

Considering the TC36x, each CPU has its own 64 KB dLMU (distributed local memory unit) and there is NO LMU memory on this device. 

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