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Hello,
I want to use the ADC1 for totally 8 analog input channels. I use "Scan Convertion Operation" and "One-shot mode for multiple channels" with "Software Start".
After starting with SSTR = 1, the Bit SCS will be polled.
After SCS is set to 0 by hardware the FIFO is sequentially read until the FIFO is empty ( SEMP = 0 ) and the convertion results are stored.
The problem is, that the result is only at 3 channels correct while the results at the other 5 channels are always 0.
What could be the reason for this behavior?
Thank you very much
Solved! Go to Solution.
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Hi Klaus,
I assume a difference in the header file of the MB9BF516N project regarding the bitband definitions (no word access) as the SCFD FIFO will only be incremented when accessing the upper 8 bit.
Attached are new templates that should not have this issue (all bitband access is 8bit where possible). But there were some bigger changes made compared to previous device header files:
- Register names were aligned between FM0+, FM3, FM4
bFM3_ADC1_SCFDL_INVL is bFM3_ADC1_SCFDL_INV
kind regards,
Achim
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Hi,
can you share your code or at least the ADC initialization?
It sounds like an initialization issue to me,
kind regards,
Achim
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Hi Achim,
thank you for your answer.
I've just found the reason for the problem.
The controller MB9BF504N makes an incorrect function.
First I polled the INV flag with
if ( bFM3_ADC1_SCFDL_INVL ) /* IF INVL == 1 */
break;
and then I read the value of the FIFO with
FifoStageVal = FM3_ADC1->SCFD;
Obviously the reading instruction with bFM3_ADC1_SCFDL_INVL reads the complete FIFO stage and increments the FIFO counter.
So only every second analog value was read. This is defenitely an incorrect function.
The use of the bit band alias mustn't use a 32 bit instruction.
By the way, the identical source code works correct with the controller MB9BF516N.
Kind regards,
Klaus
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Hi Klaus,
I assume a difference in the header file of the MB9BF516N project regarding the bitband definitions (no word access) as the SCFD FIFO will only be incremented when accessing the upper 8 bit.
Attached are new templates that should not have this issue (all bitband access is 8bit where possible). But there were some bigger changes made compared to previous device header files:
- Register names were aligned between FM0+, FM3, FM4
bFM3_ADC1_SCFDL_INVL is bFM3_ADC1_SCFDL_INV
kind regards,
Achim
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Hi Achim,
thank you for your answer and your great help.
I always thought, that fetches via the bit band alias will be done internally by hardware.
Kind regards,
Klaus
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Hi Klaus,
The fetches are done internally by the hardware when accessing the bit-band areas, but they derive their access size from the actual read command that triggered the bit-band access. This is important, as some registers are restricted in their access size, as shown in the register map at the end of the TRM.
kind regards,
Achim