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There is tRDYI as a timing parameter to enable/disable MRDY.
This parameter is related to MOEX and MCLK. It can be designed in Synchronous SRAM mode, but it cannot be designed in Asynchronous SRAM mode because MCLK is not output external. How should I design it?
Thanks,
Tetsuo
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Dear Tetsuo,
It operates based on the internal clock supplied to the External bus interface.
You can calculate and design the time width considering the phase difference and frequency error between the internal clock of the MCU and the external DEVICE clock.
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Dear Tetsuo,
It operates based on the internal clock supplied to the External bus interface.
You can calculate and design the time width considering the phase difference and frequency error between the internal clock of the MCU and the external DEVICE clock.
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Roy-san,
What does "the external DEVICE clock" mean? I can't confirm MCLK, so I think it is a different clock. Is it correct? If it is correct, please tell me what clock it is.
Thanks,
Tetsuo
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Is there any update information about my comment?
Thanks,
Tetsuo
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Tetsuo-san,
You are right. It is a different clock. "the external DEVICE clock" means the clock of input into external SRAM.
You can write in Japanese if necessary to explain this issue details.
Best regards,
Terashima
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Terashima-san、
以後、日本語で失礼します。
確認したいのは非同期SRAMモード時のtRDYIのタイミングの規定をデバイス外部からどのように確認したらよいのか(その術はあるのか)、です。
非同期SRAMモードの場合、MCLKがMCUの外に見えないので、MCLKを基準に設計ができません。RDY解除時はMRDY信号の立ち上がりをMCUが受け取り、内部でMRDY信号の立ち上がりを認識するまでにかかる時間である、と認識しましたが正しいでしょうか。
よろしくお願いします。
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今回、非同期であるため時間を考慮して設計する必要があります。
外部バスインターフェイスはMCLKで動作しておりますので、例えばDatasheetに2cyclesと記載があれば、2 * 1/Fの時間になります。(F=MCLKの周波数)
更に非同期での設計するにあたり、
- 外部SRAMの動作クロック、外部バスインターフェイスの動作クロックの位相差
- 外部SRAMの動作クロック、外部バスインターフェイスの動作クロックの誤差
も考慮してください。
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ありがとうございました。理解できました。