Version: **
Reference hardware designs of Tiger Lake platfrom for new notebooks/desktops are based on EZ-PD™ CCG5. Currently, the latest compliance test suites need firmware updates for CCG5.
This KBA describes how to pass latest compliance tests and enable the CCG6DF/SF device to work with the Tiger Lake platform. After you make the following hardware changes from CYPD5225 to CYPD6227/CYPD6228, the firmware binaries (CYPD6227-96BZXI_notebook_tgl.hex) generated by the EZ-PD™ Host SDK 3.5 example code can be used directly with the test suite.
Table 1 lists differences in device resources (hardware and firmware) between CCG5 and CCG6DF.
Table 1 Hardware and firmware features between CCG5 and CCG6DF
HW/FW |
Features |
CCG5 (2-port) |
CCG6DF (2-port) |
HW |
Package |
96-BGA (6*6 mm: 36 mm2) |
96-BGA (6*6 mm: 36 mm2) |
Power Delivery support |
Yes (Thunderbolt) |
Yes (Thunderbolt) |
|
MUX (SBU, SS, or HS) |
SBU and High Speed |
High Speed |
|
20-V protection on SBU/CC |
Yes |
Yes |
|
Includes BC1.2 Source or Sink |
BC1.2 Source only |
No |
|
VBUS Consumer path gate driver |
PFET |
NFET, OVP, S/R |
|
VBUS Provider load switch - VBUS RCP, SCP, OCP, OVP, and programmable slew rate control |
No |
Yes Improved SCP performance |
|
VBUS OCP current sense resistor |
10 mΩ |
5 mΩ |
|
VCONN RDS (on)/OCP limit |
1.5 Ω/440 mA-600 mA |
0.7 Ω/550 mA – 750 mA |
|
GPIOs/I2C interface |
28/4 |
23/4 |
|
FW |
Embedded Controller (EC) FW compatibility and USB Type-C Connector System Software Interface (UCSI) support |
Yes |
Yes |
Flash/RAM/ROM |
128/12/8 KB |
64/16/96 KB |
|
Extra ROM with stable PD code to free up flash |
No |
Yes |
|
Signed FW download |
No |
Yes |
|
Secured boot |
No |
Yes |
|
System Policy Manager |
No |
Yes |
|
USB Type-C authentication |
No |
Yes |
Based on these differences, you need to make the following hardware changes in the original reference design based on CCG5:
Figure 1 Rsense and RCP capacitance placement on CCG6DF schematic
Figure 2 VBUS Consumer schematic
CCG6DF pins |
Can be re-routed? |
D11 - I2C_SCL_SCB0/P4.0 |
No |
C11 - I2C_SDA_SCB0/P4.1 |
No |
F11 - I2C_INT_EC/P1.2 |
No |
2) CCG6DF pins connected to Tiger Lake:
CCG6DF pins |
Can be re-routed? |
H7 - I2C_SCL_SCB1/P0.3 |
No |
K9 - I2C_SDA_SCB1/P0.2 |
No |
L9 - I2C_INT_TBT_P0/P0.4 |
Yes, firmware supports re-routing |
H8 - I2C_INT_TBT_P1/P0.5 |
Yes, firmware supports re-routing |
3) CCG6DF pins connected to BB re-timer:
CCG6DF pins |
Can be re-routed? |
E10 - I2C_SCL_SCB2/P2.2 |
No. |
E11 - I2C_SDA_SCB2/P2.1 |
No. |
D10 - RETIMER_PWR_EN_P1/P2.4 |
Yes, firmware supports re-routing |
K6 - RETIMER_PWR_EN_P2/P0.1 |
Yes, firmware supports re-routing |
E8 - RETIMER_RESET_N_P1/P2.3 |
Yes, firmware supports re-routing |
L4 - RETIMER_RESET_N_P2/P0.0 |
Yes, firmware supports re-routing |
G8 - RETIMER_FORCE_PWR_EN/P1.1 |
Yes, firmware supports re-routing |
A buck controller is the perfect selection to generate the 5V output voltage from the 12V battery line. The total amount of power is 90 W (5 V, 18 A) so a synchronous buck DC-DC would help to improve the system efficiency. Moreover, due to the relative high current output demand of up to 18 A, a multiphase buck DC-DC controller would be the perfect choice in order to split the output current between two inductors and then relax the requirements for the inductors and the switching elements.
Indeed a multiphase design allows significant flexibility for output inductor choice, which is extremely important in small form factor applications because it allows selection of a device with a smaller saturation current with the consequence that smaller inductor sizes can be selected.
Another benefit of the multiphase design is to reduce the output voltage ripple by a factor n, where n is the number of phases, without the need to increase the output filter capacitance.
Moreover a multiphase design improves also the EMC performances of the DC-DC with the consequence that BOM cost can be saved by designing smaller filters.
Infineon offers the right choice for a buck multiphase voltage regulator: the TLD5501-2QV.
TLD5501-2QV is a dual channel synchronous buck DC-DC controller explicitly designed for high power applications. The two channels can work independently or in multiphase operations. It implements an SPI interface to control and retrieve the status of the DC-DC. The switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external clock source. A built-in programmable spread spectrum switching frequency modulation and the forced continuous current regulation mode improve the overall EMC behavior. Furthermore, the current mode regulation scheme provides a stable regulation loop maintained by small external compensation components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up.
The control unit hardware implementation with the TLD5501-2QV is then shown in https://www.infineon.com/export/sites/default/en/about-infineon/company/contacts/support/images/Figure1_TLD5501_USC_C.png Figure 1.
In https://www.infineon.com/export/sites/default/en/about-infineon/company/contacts/support/images/Figure2_TLD5501_USC_C.png Figure 2 the application diagram of the TLD5501-2QV as voltage supply in multiphase operation is shown.
For further information check the TLD5501-2QV datasheet, while more information on how to design a proper solution can be found in the https://www.infineon.com/dgdl/Infineon-Z8F67775974_USB-C_automotive_charging_ports_with_LITIXTM-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626f229553016faed53ace64fc ack=tapplication note.
Version: **
This KBA describes the workaround for EZ-USB™ FX3 family of devices to prevent incorrect response to a warm reset LFPS. Details include trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local sales representative if you have questions.
Part numbers affected
Part number |
Device characteristic |
CYUSB301x-xxxx CYUSB201x-xxxx CYUSB306x-xxxx CYUSB303x-xxxx CYUSB3025-BZXI CYUSB2024-BZXI CYUSB2025-BZXI |
All variants |
EZ-USB™ FX3 qualification status
In Production
EZ-USB™ FX3 summary
The following table defines the applicability to available EZ-USB™ FX3 family devices.
Items |
Part number |
Silicon revision |
Fix status |
EZ-USB™ FX3 device does not respond correctly to warm reset LFPS from the host. |
CYUSB301x-xxxx CYUSB201x-xxxx CYUSB306x-xxxx CYUSB303x-xxxx CYUSB3025-BZXI CYUSB2024-BZXI CYUSB2025-BZXI |
All revisions |
Use workaround |
EZ-USB™ FX3 device does not respond correctly to warm reset LFPS from the host. |
|
Problem definition |
When a USB host sends warm-reset LFPS, EZ-USB™ FX3 responds back with a warm-reset LFPS. As per USB 3.2 specification, warm reset LFPS should only be generated by a downstream port to an upstream port. |
Parameters affected |
NA |
Trigger condition(s) |
This condition is triggered when EZ-USB™ FX3 detects a warm reset LFPS sent by the host. |
Scope of impact |
When EZ-USB™ FX3 is connected to some hosts which use a re-timer and redriver, it is observed that the re-timer detects the LFPS from EZ-USB™ FX3 and handles it as a reset after the host has moved to the Rx detect state. This may cause the redriver to move to the U1 state resulting in link training failure. |
Workaround |
EZ-USB™ FX3 receives a state change interrupt whenever there is a LTSSM state change in the device. EZ-USB™ FX3 transitions to LTSSM reset state when it detects a warm reset LFPS. This state change interrupt is used to halt LFPS transmission till the device has reached LFPS polling state. It is observed that EZ-USB™ FX3 no longer transmits a warm reset LFPS signal in response to a detected warm reset after this workaround. The workaround is implemented in EZ-USB™ FX3 SDK v1.3.5.54 and the compiled libraries with this workaround are attached with this KBA. |
Fix status |
Suggested firmware workaround is tested and reliable. |
Attachments
EZ_USB_FX3_SDK_1_3_4_54_files.zip - Contains the compiled EZ-USB™ FX3 libraries and two code examples that use these library files.
Video stream not visible while streaming through EZ-USB™ CX3
Do the following to debug:
Note: If UART cannot be used to get the debug prints, use the firmware attached with this KBA. With this firmware, the device enumerates as a composite device with CDC + UVC interface. Use serial terminal like Tera Term or any other application and then start the UVC host application.
Criteria to check in the debug prints |
Actions if criteria are not satisfied |
MIPI errors are 0 |
1. Ensure that the MIPI CSI2 routing guidelines mentioned in Q8 of this KBA91295 are followed. 2. Confirm that the MIPI transmitter is MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2nd April 2009) Note: If the MIPI CSI clock used is continuous clock, see Q13 of this KBA91295. For details on MIPI errors, see KBA228482.
|
The frame size received by EZ-USB™ CX3 is the same as the frame size reported in the USB descriptor for the particular resolution. |
1. Check whether the MIPI transmitter is configured with the same settings as the CX3 MIPI receiver configuration tool. 2. Verify whether the HSYNC and VSYNC signals on the test points (mentioned in Q10 of this KBA91295) behave correctly per the chosen resolution and frame rate. 3. Check whether there are any errors thrown by the CX3 MIPI receiver configuration tool. Note: The maximum CSI clock frequency should be used per Q13 of this KBA91297. Check whether the image throughput [bits per pixel × (Horizontal resolution + Horizontal blanking) × (Vertical resolution + vertical blanking) × frames per second] is less than or equal to the GPIF throughput [output pixel clock * GPIF_BUS_WIDTH]. 4. Confirm that the output video format of the CX3 configuration tool and GPIF_BUS_WIDTH is configured with the same setting. 5. If you select the video format as “RAW” (RAW8/RAW10/RAW12/RAW14) in the CX3 configuration tool, you cannot use the UVC player to display the RAW data. However, the RAW data can be streamed as 16-bit/24-bit data by treating them as YUV format/ RGB888 format respectively. Note: For streaming RAW video format, see this KBA224387, which provides details on firmware modifications needed for padding/packing of the RAW video data. Note that the image will look green in color due to the mismatch in image formats. This method can be used for firmware development and testing.
|
DMA reset events are observed in the debug prints |
1. If the DMA reset event is due to a callback failure “CB failure”, see this KBA231382. 2. Check if the handling of the DMA reset event done in the firmware as per this KBA218830. 3. If the DMA reset event is due to video timer, check if the V_Total (V_Active + V-Blanking) period is more than TIMER_PERIOD defined in the firmware. 4. If the DMA reset is still happening and is not due to one of these two reasons, then check if the image throughput is less than or equal to the GPIF throughput (output pixel clock * GPIF_BUS_WIDTH). |
This function is used to set the CX3_PHY_TIME_DELAY register values. See EZ-USB™ CX3 TRM for details on this register. This function should be not be called while the MIPI-CSI PLL clocks are active. Either call this API after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before calling CyU3PMipicsiWakeup()), or call CyU3PMipicsiSleep() before calling this API.
Figure 1 Phy time delay value from CX3 MIPI receiver tool
(The second byte of the header is either 0x8E or 0x8F for the end-of-frame transfer). The total image data transferred in a frame (not including the UVC header) should be: width * height * pixel size in bytes. See points 4,5,6, and 12 of this KBA226722. These points are applicable to EZ-USB™ CX3. If this is not the amount from the USB trace, there may be an issue with the MIPI interface; that is, a mismatch in the MIPI transmitter and CX3 MIPI receiver settings.
Do the following:
Related Categories:
Keywords: CX3, Trouble Shooting
Product Family: CyUSB306x
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|
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|
|
MCU: CAPSENSE
Capsense |
|||||
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MCU: RTOS
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|||||
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|
MCU: SOFTWARE
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|
|
|
|
|
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|
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|
MCU: BLE
BLE |
|
|
|
|
|
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` |
|
|
|
MCU: Bootloader
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|
|
|
|
|
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|
|
|
|
MCU: Security
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|
|
|
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|
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|
|
|
MCU: MM MCU
MM MCU |
|
|
|
|
|
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|
|
|
|
MCU: General
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SMP |
SPI |
System Level Design |
Timer |
UART |
USB |
USBUART |
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|
|
Automotive : TRAVEO
ADC |
A/D Converter |
|
|
|
|
Bus Interface |
AHB |
AXI |
External Bus |
TCM |
|
BootROM |
|
|
|
|
|
CAN |
CAN FD |
MRAM |
|
|
|
Clock |
|
|
|
|
|
Calibration |
Clock gear |
CSV |
Clock supervisor |
Fast CR |
PLL |
Phase Locked Loop |
Slow CR |
SSCG PLL |
Spread Spectrum Clock Generator PLL |
Stabilization |
|
CPU |
CRC |
Cache |
Cortex-R5 |
Store Buffer |
DMA |
EAM |
Exclusive Access Memory |
|
|
|
|
ECC |
Error Correction Code |
Error Injection |
SECDED |
Ethernet |
|
Exception |
Abort |
NMI |
FlexRay |
||
Graphics |
APIX |
FPD link |
LCDC |
LVDS |
IRIS |
GPU |
VRAM |
|
|
|
|
Hyperbus |
HyperFlash |
HyperRam |
|
|
|
ICU |
Input capture unit |
I2C |
|
|
|
Interrupt |
VIC |
Vectored Interrupt Controller |
LIN |
LVD |
|
MCAL |
AUTOSAR |
BASE |
CRY |
DEM |
DET |
FEE |
FLS |
GPT |
ICU |
MCU |
MAKE |
PORT |
PWM |
RESOURCE |
WDG |
Coretst |
Memtst |
Ramtst |
Flstst |
|
|
|
|
Media LB |
|
|
|
|
|
MFS |
Multi-Function Serial |
|
|
|
|
Mode |
Mode pin |
|
|
|
|
Motor Control |
SMC |
Stepper Motor Control |
MPU |
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OCU |
Output Capture unit |
Port |
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Power |
Power Domain |
PD1 |
PD2 |
PD4 |
PD6 |
PSC_1 |
PSC1 |
PSS PSS Stop mode |
PSS timer mode |
PSS Shutdown mode |
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Programming |
Flash Programmer |
Parallel programming |
FPRG |
PPU |
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RAM |
Backup RAM |
Scratch Pad Ram |
System Ram |
TCRAM |
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Reset |
Power ON Reset |
Software reset |
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RTC |
Real Time Clock |
Safety |
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Security |
Secure Boot |
AES-128 |
SHE |
CRYPTO |
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Sound |
Audio DAC |
I2S |
PCMPWM |
Stereo Audio DAC |
Waveform Generator |
Sound Mixer |
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SPI |
CSIO |
Startup |
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TCFLASH |
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Timer |
Base Timer |
Indicator PWM |
RLT |
Reload Timer |
UDC |
QPRC |
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TPU |
UART |
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Watchdog |
Hardware watchdog |
Software watchdog |
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WorkFlash |
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Automotive: TRAVEO II
ADC |
Calibration |
SAR ADC |
Bootloading |
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BootRom |
Boot |
Internal Bootloading |
Flash Boot |
Multicore Boot |
ROM |
ROM Boot |
Secure Boot |
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Bus Interface |
AXI |
AHB |
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CAN |
CANFD |
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Clock |
Clock Tree |
CSV |
External Clock |
FLL |
PLL |
systick |
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CPU |
Cortex M0+ |
Cortex M4 |
Cortex M7 |
Cross Trigger |
CXPI |
Debugger |
DAP |
Program and Debug IF |
SWD |
JTAG |
Trace |
DMA |
Data Wire |
Descriptor |
MDMA |
PDMA |
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ECC |
Error Injection |
SECDED |
parity |
syndrome |
EFUSE |
EVTGEN |
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Exception |
Bus Fault |
Hard Fault |
Memory management |
Fault NMI |
PendSv |
Supervisor Cal |
Usage Fault |
Fault |
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Flash |
CodeFlash |
Dual Bank |
FOTA |
Memory Bank |
WorkFlash |
Flexray |
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Interrupt |
Interrupt Synchronizer |
WIC |
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IOSS |
Drive mode |
HSIO |
HSIOM |
IO Subsystem |
Slew rate |
Smart I/O |
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IPC |
Interrupt Structure |
Message Passing |
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Lifecycle state |
Chip operation mode |
VIRGIN |
SORT |
NORMAL |
NORMAL_PROVISIONED |
PROVISIONED |
SEC_W_DEBUG |
SECURE |
CORRUPTED |
Protection state |
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LIN |
PID |
LVD |
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Market Segment |
Body Control |
Chassis |
Cluster |
Gateway |
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MCAL |
AUTOSAR |
BASE |
CRY |
DEM |
DET |
DIO |
FEE |
FLS |
GPT |
ICU |
MCU |
MAKE |
OCU |
PORT |
PWM |
RESOURCE |
WDG |
Coretst |
Memtst |
Ramtst |
Flstst |
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MMIO |
Motor Control |
MPU |
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Power |
Brown out |
Deep Sleep |
Hibernate |
Power mode |
PPU |
Programming |
Cypress Programmer |
Miniprog4 |
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Protection Context |
Protection State |
Protection Structure |
Reset |
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RTC |
Alarm |
Safety |
SCB |
SDIO |
SDHC |
Security |
Crypto |
SLLD |
AES |
CHACHA |
TDES |
SHA |
CRC |
STR |
PR |
TR |
PRNG |
TRNG |
VU |
SHA1 |
SHA2 |
SHA3 |
DES |
SMIF |
Dual Quad |
Octal SPI |
XIP |
SMPU |
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Sound |
Audio DAC |
Mixer |
Sound Generator |
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SRAM |
Write Buffer |
SWPU |
System Call |
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|
TCPWM |
Dead time |
PWM |
Timer mode |
Capture mode |
Quadrature Decoder mode |
Trigger Multiplexer |
WDT |
MCWDT |
Watchdog Reset |
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MPN |
CYT2B7 |
Traveo II |
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Automotive HMI:
EMC |
EMI |
BCI |
Functional Safety |
ASIL |
ESD |
CAN |
LIN |
CXPI |
ISO-26262 |
grounded water rejection |
AEC-Q100 |
IEC-61967 |
IEC-62132 |
CISPR-25 |
ISO-11452 |
EN61000 |
glove |
wet finger |
fat finger |
large object |
multichip |
FPC |
finger threshold |
finger print |
ONS |
MDBP |
TrueTouch |
Gen4 |
Gen4L |
Gen4XL |
Gen6 |
Gen6L |
Gen6XL |
Gen7 |
Gen7L |
Gen7XL |
TSG |
TTHE |
CY8CTMA |
CYAT |
CY3295 |
TT bridge |
MTK |
Heatmap mode |
Tuning |
TTDA |
haptic |
force touch |
ITO |
Incell |
Secondary Host Interface |
display |
hover |
crypto |
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WiFi:
Middleware |
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AMQP |
MQTT |
CoAP |
AVS |
AWS |
Azure |
Homekit |
ADK |
Bonjour |
u8g/ugui/emwin |
WICEDFS |
|
WiFi Protocols |
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HTTP |
TFTP |
mDNS |
SSDP |
SNTP |
SMTP |
Gedday |
Websocket |
AGO |
P2P |
WiFi Direct |
DHCP |
RSDB |
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Security |
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TLS |
DTLS |
Enterprise Security |
WPS |
WPAx |
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OS / RTOS |
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FreeRTOS-LwIP |
ThreadX-NetX-Duo |
Amazon FreeRTOS |
mbed |
Linux |
Android |
Regulatory |
CLM |
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OTA |
OTA2 |
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WiFi Applications |
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apsta |
BT-WiFi gateway |
WLAN Audio |
Soft AP |
WICED Application framework |
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Power Save |
WLAN Powersave |
Host powersave |
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WiFi Tools |
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|
i-perf |
Throughput |
WL Tool |
Toolchain compilation |
|
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WiFi Driver & Hardware |
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SDIO |
WWD/WHD |
FMAC/ DHD |
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BSP |
Peripherals |
CoEX |
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IDE |
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WICED Studio |
Modus Toolbox |
|
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BTBLE
BLE Profiles |
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BLE |
BLE OTA |
ibeacon |
Observer |
Remote control |
Mesh |
BT Profiles |
|
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BT Audio |
BR/EDR |
A2DP |
HFP |
Headset |
SPP |
Peripherals |
|
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|
|
I2S/PCM |
HCI UART |
PUART |
Aclk |
|
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Power Modes |
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Tx power |
Low power |
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RTOS & Middleware |
middleware |
RToS |
|
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Debug |
Rfcomm |
Buffer pool |
hcd/btp/cgs file |
platform file |
memory map |
Recovery |
Jtag debug |
|
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|
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Test Tools |
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|
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Client control |
BTspy |
Chipload |
RF test |
Android App |
|
IDE |
|
|
|
|
|
WICED SMART |
WICED Studio |
Modus tool box |
Linux Host |
|
|
Stack |
BT |
BLE |
|
|
|
Device Type |
Discrete BT |
Embedded Host Discrete BT |
WiFi BT Combo |
|
|
USB
FX3 /FX3S |
|
|
|
|
|
UVC |
Slave fifo |
I2C |
UART |
SPI |
I2C |
DMA |
Socket |
GPIF II |
I2S |
JTAG / debugging |
ARM926EJ -S |
SDK |
ADMUX |
bootloader |
mass storage |
SD |
Emmc |
Storage port |
RAID |
|
|
|
|
GX3 |
Ethernet |
Driver |
Config Utility |
|
|
FX2LP |
GPIF |
8051 |
Keil uVision |
I2C |
UART |
Hardware |
|
|
|
|
|
Schematic |
layout |
crystal |
power supply |
EMI/ESD |
DVK/RDK |
Host application |
|
|
|
|
|
C/C++ |
cyapi |
.net |
driver |
control center |
streamer |
cyusb |
dll |
library |
|
|
|
AT2LP |
ATA commands |
CF Card |
|
|
|
HUB |
HX3 |
HX2 |
Shared link |
aca |
ghost charging |
power management |
|
|
|
|
|
enCore |
encore |
EnCoreII |
EnCoreIII |
EnCoreV |
keyboard |
mouse |
hid |
|
|
|
|
CX3 |
|
|
|
|
|
mipi protocol |
configuration utility |
I2C |
SPI |
UART |
bootloader |
Type C & PD:
Active cable |
Alternate mode |
CC Bootloader |
CCGx Host SDK |
CCGx Power SDK |
Charge-Through Dongle |
CY4500 PD Analyzer |
CY4521 |
CY4531 |
CY4532 |
CY4541 |
Display port |
Dock |
Dock Management Controller |
Dongle |
DR swap |
DRP |
Dual firmware image |
EMCA |
Fast role swap |
Host Processor Interface |
I2C Bootloader |
OCP |
OVP |
Passive cable |
PD3.0 |
Power Adapter |
Powerbank |
Power Delivery |
PPS |
PR Swap |
Provider |
RCP |
SBU |
Signed Firmware |
USB 3.1 Gen 1 |
USB 3.2 Gen 2x2 |
UVP |
VBUS FETs |
VCONN |
VCONN swap |
VDM |
HX3PD |
Analog Feedback |
BCR |
Config cable |
Configuration Channel |
CY4533 |
DP modes |
Gate driver |
HPD |
PAG1P |
PAG1S |
PCIe |
PD2.0 |
PDO |
RDO |
SWD |
Thunderbolt 3 |
|
Knowledge Base Article Type:
KB Type-1 |
KB Type-2 |
Compiler |
ByteCraft |
Imagecraft |
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Keil |
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HiTech |
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Component Development |
Training/Things you should know |
Component Architecture |
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Component/Project management |
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Datapath |
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Analog components |
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Digital components |
|
Component software/tools |
|
Component Testing |
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Development Kits |
FirstTouch Kit |
Development Tools |
|
Device Drivers |
Pullability |
Mass Storage |
|
Device Programming |
PSoC Programmer |
Documentation |
|
Firmware |
|
General |
|
Hardware |
Digital |
Specifications |
|
Analog |
|
Known Problems and Solutions |
|
Microcontrollers |
8051 |
M8 |
|
M8C |
|
Traveo |
|
Traveo II |
|
FCR4 |
|
FR |
|
16FX |
|
Modules |
Automotive Power Management ICs (PMICs) |
Automotive CXPI |
|
Platforms |
MacOS X |
Windows |
|
Protocols |
HID |
I2C |
|
Quality |
|
Reference Designs |
|
Software |
PSoC Designer |
PSoC Creator |
|
User Modules |
Analog |
Digital |
Document History
Document Title: EZ-USB™ CX3 troubleshooting guide - KBA233853
Document Number: 002-33853
Rev. |
ECN No. |
Description of Change |
** |
7381334 |
New knowledge base article |
Version: **
Infineon recommends that you isolate the sensor from vibration sources. The operating frequency of the sensor is 40 Hz. If vibration is expected at exactly 40 Hz with very high acceleration (≤ 0.3 g), you should do the following to minimize the vibration impact:
However, for a typical application, the impact of vibration is minimal. As shown in Figure 2, for a test setup with three sensors mounted on a commercially available air purifier, the test result shows that with the denoiser filter enabled, the sensor is robust against the vibration generated by a different fan of the air purifier.
Figure 2. Vibration robustness of XENSIVTM PAS CO2
For more details, visit the CO2 sensor website and see the application note, General design in guidelines for XENSIV™ PAS CO2 sensor.
Figure 3. Impact of CO2 on the human body at various concentration levels
Source
One such setup is as follows:
Evaluation kits are already available with major distributors.
Figure 4. Average power consumption
For more information, see Section 3 of the application note, XENSIV™ PAS CO2 for low-power applications.
With the automatic baseline offset correction (ABOC) feature enabled, the sensor accuracy drifts by 1% every year.
Figure 5. Values of pressure and acoustic stability
See Section 4.1.5 - Transfer function table in the datasheet.
Each sensor is calibrated during our production for the complete operating range. Production calibration is done with highly accurate CO2 gas bottle and verified with an ideal reference sensor.
The sensor might show small amount of offset after assembly due to stress generated from the assembly process on the light source. Therefore, to get the best performance, this offset should be corrected using either FCS or ABOC.
For the FCS calibration, you need to have a reference sensor. In the ABOC mechanism, the device keeps track of the minimum value recorded over a week. The offset to the reference baseline is computed and used to calculate the correction factor to be applied for the week after.
Figure 6. Operation of the ABOC feature
See the application note, After-assembly calibration scheme for XENSIV™ PAS CO2 for more details.
Figure 7. Airflow direction
See the application note, General design in guidelines for XENSIV™ PAS CO2 sensor for details.
Note: For more information, see the Community webpage for CO2 sensor where you can find answers to your questions and ask your own.
Author: Ashwin Nair Version: **
The EZ-USB™ FX3 Explorer kit can be used as a 16-channel 100 MHz USB 3 logic analyzer with sigrok PulseView. (Note that the following steps are applicable for any FX3 device. Explorer kit is used in this KBA, as all the IOs needed are exposed in this kit as shown in Figure 1).
This KBA lists the steps required to use the FX3 Explorer kit as a logic analyzer with PulseView.
Steps:
Figure 2. cypress-fx3 in the list of supported hardware devices
Figure 3. Download Image file to onboard I2C EEPROM
Figure 4. Bind FX3 device to WinUSB
Figure 5. Scan for cypress-fx3 devices
Figure 6. Using SPI Decoder to decode captured signals
Note:
Download the following files from FX3.zip:
Author: Mitilesh Version: **
The EZ-USB™ SX3 HDMI 4K Capture Card is a USB Video Class (UVC), USB Audio Class (UAC) compliant capture card which is ideally suited for capturing video and audio from any HDMI source and supports up to 4K, 30fps/ 1080p, 60fps in YUV format video. It is based on Infineon® EZ-USB™ SX3, a USB3.1 peripheral controller, Lattice ECP5 FPGA and HDMI receiver IC.
Figure 1. SX3 HDMI RX 4K capture card block diagram
Any HDMI source such as Laptop, Raspberry Pi, Gaming consoles, Android TV set-top box, media streaming devices like Amazon fire TV, Apple TV, and so on can be used with this kit. The “Microsoft Camera” application, e-CAMView, MPC-HC player or any UVC player application can be used to view this video on a USB Host. This is a form factor kit of size 26-mm × 75-mm.
The kit schematic, BOM, and board files are attached with this document. You can build customized board using these files.
The kit firmware configuration file includes the SX3 configuration and FPGA bit file which are attached with this document.
Figure 2. EZ-USB™ SX3 HDMI 4K capture card - Rev 01
Figure 3. Type-C and HDMI receptacles of EZ-USB™ SX3 HDMI 4K capture card – Rev 01
Follow the below steps to capture the 4K video from HDMI source using EZ-USB™ SX3 HDMI 4K Capture Card:
Figure 4. Import configuration option in SX3 configuration utility
Figure 5. Program configuration option in SX3 configuration utility
Figure 6. SX3 devices in Device Manager after Enumeration
Figure 7. Video played on HDMI source viewed in Windows camera application
Figure 8. Testing the audio from HDMI source
Figure 9. Enable “Listen to this device” option to route audio from HDMI source to the speaker
Steps to re-program the EZ-USB™ SX3 HDMI 4K Capture Card
In EZ-USB™ SX3 HDMI 4K Capture Card Revision 01, there is no provision available to change the boot option using PMODE pins. To re-program the board, the device will need to boot as USB Bootloader Device.
To erase the on-board firmware and to get back the device to bootloader mode, open the command prompt in the folder where HID_Sample_App.exe is located and enter the reset command as shown below:
HID_Sample_App.exe -vid 0x04b4 -pid 0x00c2 -reset
Replace the vid and pid values with corresponding vendor ID and product ID of the connected device. Once it is successful, the “Erase and Fallback to Bootloader is successful” message is displayed as shown in the below screenshot.
Figure 10: Reset the existing firmware using HID_Sample_App.exe
Download the HID_Sample_App.exe file from the attachments. Once the board falls back to bootloader mode, follow the procedure from step 2 to program the device.
Additional learning resources:
Visit www.cypress.com/sx3 for additional resources like datasheet, and application note, configuration utility user guide.
Attachments with EZ-USB™ SX3 HDMI 4K Capture Card Solution Demo Kit:
Version: **
The CCGx Power SDK 3.5 example firmware provides two ways:
1. Change the Retry count from 2 (default value) to 255 by using the EZ-PD™ configuration utility, and then save the configuration into firmware .hex/.cyacd file directly. You can also replace the config.c file in the firmware project and rebuild it.
2. Change the config.h file in firmware project directly without configuration table changes on Over Current Protection and rebuild the firmware project.
Version: **
The PD negotiation occurs with the sink looking for the source PDO which matches the voltage according to its own capabilities, starting from the highest PDO. Depending on the current in the source PDO, two things can happen:
Section 6.4.2.3 of the Power Delivery specification R3 states as follows:
Capability Mismatch occurs when the sink cannot satisfy its power requirements from the capabilities offered by the source. In this case, the sink shall make a valid request from the offered capabilities and shall set the “Capability Mismatch” bit.
When a sink returns a Request Data Object in response to the advertised capabilities with this bit set, it indicates that the sink wants power that the Source cannot provide. This can be due to either a voltage that is not available or the amount of available current. At this point, the source can use the information in the request message combined with the contents of the Sink_Capabilities message to verify the voltage and current required by the sink for full operation.
When these operations are performed, a valid Request Message means the following:
Sink_Capabilities message.
4. If the GiveBack flag is set to ‘1’, i.e., there is a Minimum Operating Current/Power field:
This example requires the following:
1) CY4532 EZ-PD CCG3PA evaluation kit
2) CY4500 EZ-PD protocol analyzer
3) CY4533 EZ-PD barrel connector replacement (BCR) evaluation kit
Block diagram of the setup:
Source 1 PDO available: 5V@3A and 10V@ 3A
Figure 1. Source 1 PDO capabilities
BCR sink requirement: 12V
Because the available Source PDOs were 5V and 10V, the negotiated voltage was 10V which is according to the PD specification.
Figure 2. BCR Sink capability mismatch and PDO request
Source 2 PDO available: 5V@ 3A and 13V@ 3A
Figure 3. Source 2 PDO capabilities
BCR sink requirement: 15V@ 3A.
Because the available Source PDOs were 5V and 13V, the negotiated voltage is 13V, which is according to the PD specification.
Figure 4. BCR Sink capability mismatch and PDO request
Original KBA: Common Errors while Programming CCG3PA using EZ-PD Configuration Utility - KBA232322
Translated by: Kenshow
==============================
タイトル: EZ-PDコンフィグレーションユーティリティを使用してCCG3PAをプログラミングする際の一般的なエラー - KBA232322
バージョン: **
質問: EZ-PDコンフィグレーションユーティリティを使用してCCG3PAをプログラミングするときに発生する一般的なエラーは何ですか?
回答: EZ-PDコンフィグレーションユーティリティは、ユーザーがCCGxコントローラを構成およびプログラムするのに役立つMicrosoftWindowsアプリケーションです。グラフィカルユーザーインターフェース(GUI)を使用すると、ユーザーはアプリケーションのさまざまなパラメータを直感的に選択して構成できます。
EZ-PDコンフィグレーションユーティリティとインストーラーの詳細については、https://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utilityにアクセスしてください。
CY4532 EZ-PD CCG3PAEVKでのプログラミング設定
CY4532 EZ-PD CCG3PA EVKは、CCG3PAコントローラを備えたメインボードと、メインボードに必要な電源を供給する電源ボードで構成されています。電源ボードもサイプレスCCG4コントローラで構成されており、EZ-PDコンフィグレーションユーティリティを使用してメインボードにあるCCG3PAにファームウェアをダウンロードできます。CCラインを使用してCCG3PAデバイスに接続されます。CCG4コントローラはI2Cを介してサイプレスUSBシリアルデバイス(電源ボード上にあります)に接続され、EZ-PDコンフィグレーションユーティリティからCCG3PAファームウェアを受信します。CY4532EVKでCCG3PAコントローラをプログラムするために必要な接続を図1に示します。
図1. CY4532EVKでのCCG3PAコントローラプログラミングセットアップ
プログラミング中の一般的なエラー
以下は、EZ-PDコンフィグレーションユーティリティを使用してCCG3PAをプログラミングしているときにユーザーが遭遇する一般的なエラー、考えられる理由、および解決策です。
図2. EZ-PDコンフィグレーションユーティリティでメインボードが検出されない
表1. プログラミング中のメインボードの検出エラーの解決策
問題/エラー |
理由/正当性 |
回避策 |
EZ-PDコンフィグレーションユーティリティはデバイスを検出できません。電源ボードはコンフィグレーションユーティリティによって検出されますが、プログラムされるデバイスは検出されません。 |
プログラムする電源ボードとメインボードが正しく接続/電源供給されていない |
デバイスと電源ボード間の接続が有効であり、電源ボードに適切に電力が供給されていることを確認してください。 |
|
CY4532EVKのジャンパー設定が無効です |
CY4532EVKガイドの説明に従ってジャンパーが接続されていることを確認してください |
図3. メインボード上のCCG3PAコントローラがEZ-PDコンフィグレーションユーティリティでグレー表示されている
コンフィグレーションユーティリティログ:
PD contract established.
Error: No response to GET_SILICON_ID U_VDM
Retrying, ignore the above error message
Error: Flashing VID (4b4) not found in Discover SVID Response
表2. プログラミング中にデバイスが非アクティブ化されるというエラーの解決策
問題/エラー |
理由/正当性 |
回避策 |
プログラムするデバイスはグレー表示されており、ファームウェアの更新中にEZ-PDコンフィグレーションユーティリティで選択することはできません。
|
Device Parametersタブの[Enable firmware update]を[No]に設定すると、コンフィグレーションテーブルでCCインターフェースを介したファームウェアの更新が無効になりました |
コンフィグレーションテーブルの「Enable firmware update」セクションを「Yes」に設定する必要があります。この新しいファームウェアは、CCG3PASWDインターフェースを使用してプログラムする必要があります。これにより、EZ-PDコンフィグレーションユーティリティからCCインターフェースを介してファームウェアの更新をさらに実行できます。 |
図4. EZ-PDコンフィグレーションユーティリティでのファームウェア更新の失敗
表3. ファームウェアの更新に失敗した場合の解決策
問題/エラー |
理由/正当性 |
回避策 |
ファームウェアの更新は30%完了で停止し、EZ-PDコンフィグレーションユーティリティログで更新エラーの有効なファームウェアが見つかりませんでした。 |
コンフィグレーションテーブルの.cyacdファイルを使用してファームウェア全体を更新した場合に発生します。 |
PSoC Creatorのプロジェクトが構築されているとき、2つの別々の.cyacdのファイルが作成されます。Project_name.cyacdをプログラムすることが全体のファームウェアイメージが含まれているとProject_name_config.cyacdは、プロジェクトの構成のみテーブルが含まれています。新しいファームウェアのプログラミング中は必ずProject_name.cyacdを選択し、コンフィグレーションテーブルの更新中はProject_name_config.cyacdを選択してください。 |
表4. フラッシュ更新エラーの解決策
問題/エラー |
理由/正当性 |
回避策 |
フラッシュアップデート手順が失敗すると、ファームウェアアップデートは90%/ 99%完了で停止します。RESETエラーメッセージの後にPDコントラクトを確立できませんでした。 |
FWの更新後にPD契約が確立されていません。プログラムされた新しいファームウェアが機能しない可能性があります。その場合、CCインターフェースを介した将来のファームウェアアップデートは不可能です。 |
ブートローダーでテスト済みの動作中のファームウェアは、SWDインターフェースを介してプログラムする必要があります。再プログラミング時に、EZ-PDコンフィグレーションユーティリティを使用してデバイスを再度プログラミングできます。 |
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デバイスは、「Enable firmware update」パラメータを「No」に設定することにより、コンフィグレーションテーブルで将来のファームウェア更新を無効にしてプログラムされています。 |
この場合、それは予想される動作です。新しくプログラムされたファームウェアが期待どおりに機能しているかどうかをテストします。 |
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CY4532 EVKでは、これは、新しいファームウェアが以前のアプリケーションとは異なるアプリケーション(電源バンク/電源アダプタ)からのものである場合に発生します。 |
これは予想される動作です。新しくプログラムされたアプリケーションごとにジャンパー設定を変更し、それが機能しているかどうかをテストします。 |
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FWの更新後にPD契約が確立されていません。UFP再起動タイムアウトの値を小さくすると、問題が発生する可能性があります。 |
UFP再起動タイムアウト値は、オプションメニューで増やすことができます。 |
図5. 破損したファームウェアでプログラムしたときに表示されるエラーメッセージ
表5.フラッシュ更新手順の失敗によるエラーの解決策
問題/エラー |
理由/正当性 |
回避策 |
更新されたファームウェアイメージが無効です。フラッシュ更新手順が失敗しました。 |
使用したファームウェアファイルが破損しています。図5のようにエラーメッセージが表示されます。 |
データが破損していない動作中のファームウェアは、SWDインターフェースを介してプログラムする必要があります。 |