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Question:
How to create a basic PSoC^® Creator project implementing UART functionality, without using UART component in TopDesign.cysch?

Answer:
The Universal Asynchronous Receiver/Transmitter (UART) protocol is an asynchronous serial interface protocol. UART communication is typically point-to-point. The interface consists of two signals: transmitter output and receiver input signals. Implementing UART functionality without UART component is useful in the scenarios, when there is a requirement to share hardware resources for different functionalities.

To implement this in the PSoC^® Creator project, there is a need to add all the relevant source files for UART functioning. These files should be included in the ‘Source files’ folder of the PSoC^® 6 core, where the UART program will be executed. These files are mentioned below -

1. To begin with, cy_scb_uart.h header file provides UART API declarations of the SCB driver and cy_scb_uart.c provides UART API implementation of the SCB driver.
2. UART.c file is added to provide the source code to the APIs of the UART component and UART.h header file defines the necessary constants and parameter values for the UART component.
3. UART_SCBCLK.h file takes care of the source code to the APIs for the UART_SCBCLK component.
4. The two files cy_scb_common.h and cy_scb_common.c files are added to the common APIs of the SCB driver and also for the proper implementation of the other linked header files such as cy_scb_uart.h.

Note: The above files can be used from the “Generated files” folder of an existing project, that has a UART component in TopDesign.cysch.

A basic PSoC^® Creator project implementing the above has been explained further. It aims at printing the statement “Working in UART mode” in the serial terminal, without using the UART component in TopDesign.cysch.

1. Add the necessary source files as explained above under the CM4 (core 1) of PSoC^® 6 as shown in Error! Reference source not found..
   
   Figure 1 Source files for UART
2.  Include “UART.h” header file in the main.c to include all the API usage for UART functionality.
3. The GPIO pins are configured to function as UART pins. The HSIOM register must be configured to connect dedicated SCB UART pins to the SCB block. Also, the UART output pins must be configured in Strong Drive Input off mode and UART input pins in Digital high-Z. This is shown in the below code:
   
   

   /* Assign pins for UART on SCB5: P5[0], P5[1] */
   #define UART_PORT               P5_0_PORT
   #define UART_RX_NUM             P5_0_NUM
   #define UART_TX_NUM             P5_1_NUM
   

   /* Connect SCB5 UART function to pins */
   Cy_GPIO_SetHSIOM(UART_PORT, UART_RX_NUM, P5_0_SCB5_UART_RX);      Cy_GPIO_SetHSIOM(UART_PORT, UART_TX_NUM, P5_1_SCB5_UART_TX);   

   /* Configure pins for UART operation */      Cy_GPIO_SetDrivemode(UART_PORT, UART_RX_NUM, CY_GPIO_DM_HIGHZ);
   Cy_GPIO_SetDrivemode(UART_PORT, UART_TX_NUM, CY_GPIO_DM_STRONG_IN_OFF);

4. A clock source must be connected to the SCB block to oversample input and output signals. The system clock driver APIs are used to provide the UART clock divider type and number.
   

   /* Assign divider type and number for UART */
   #define UART_CLK_DIV_TYPE      (CY_SYSCLK_DIV_8_BIT)
   #define UART_CLK_DIV_NUMBER    (0U)

   /* Configure clocks for UART operation */
   Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER);

5. To get the UART to operate with the desired baud rate, the clk_scb frequency and the oversample must be configured. For example, in this project the baudrate is set to 115200 bps(standard mode). The calculation is explained below:
   

   UART baud rate = (clk_scb/oversample)
   For clk_peri as 50 MHz, the divider value = 36 and get clk_scb (SCB Clock) = (50 MHz / 36) = 1,389 MHz.
   Select oversample = 12. These setting results in UART data rate = 1,389 MHz / 12 = 115750 bps.
   /* Configure Baudrate for UART operation */     
   Cy_SysClk_PeriphSetDivider   (UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER, 35UL);
   Cy_SysClk_PeriphEnableDivider(UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER);

6. The initialization code for the UART block uses the configuration structure as shown below:
   

   /* Initialize the UART operation */
   cy_en_scb_uart_status_t uart_status;
   uart_status = Cy_SCB_UART_Init(UART_HW, &UART_config, &UART_context);
   Cy_SCB_UART_Enable(UART_HW);

7. Perform printing of the statement inside for loop() for the output of the project as shown in Figure 2.
   

   Figure 2 Printing on the serial terminal

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You cannot use S29GL256S as primary booting memory for Xilinx Zynq-7000 SoC because S29GL256S supports x16 data width and does not have an x8 option. The Xilinx Zynq-7000 SoC supports NOR flash with x8 data width only.

However, S29GL512T does have an x8/x16 option, so it can be used as the primary booting memory for Xilinx Zynq-7000 SoC.

The TLD5542-1QV has a fast discharge feature that allows to quickly discharge the output capacitor. During a fast discharge phase the ouput capacitor is getting discharged to the input capacitor and therefore causing a small reverse input current.

The figure below shows the switching pattern and waveforms during this fast discharge phase.

Read more on fast discharge in the datasheet https://www.infineon.com/dgdl/Infineon-TLD5542-1QV-DataSheet-v01_10-EN.pdf?fileId=5546d4626fc1ce0b016ff1ac705d4601 on pages 27 and 28.

The TLD509x mainly differ in maximum output voltage, output current accuracy, analog dimming, short-to-ground protection and capability to drive an external NMOS for dimming purpose from each other: 

The status functionality of the TLE4242 is unlatched.

When a fault is detected by one of the devices, this one pulls down the ST pin using an open collector circuit. This pulls down the connected PWM pin of the second device and brings it into sleep mode.

When the fault condition is removed the device which has detected the fault releases the ST pin (open collector output off) and the ST pin voltage rises again. The second device connected with its PWM pin to this ST pin is then activated again and both devices are back in normal operation.

In case of a resistive load (e.g. 50 Ohm) is connected to the output of an linear current source instead of real LEDs and the supply voltages increases slowly the output channel may not turn on.

Basic and Basic+ LED drivers are not designed for driving pure resistive loads. In case the output voltage VOUT is below the required output voltage for current control VOUT(CC) (see parameter 7.2.7 in the datasheet) the  main power stage is operating with the short circuit protection mechanism integrated in our LED drivers. At start-up when VOUT < VOUT(CC) the device uses a startup current of a few 100 µA to rise the output voltage. Once the output voltage is above VOUT(CC) the main current control loop is starting to work and the target current is flowing.

Recommendation would be change the load to add diodes in series to the resistor to achieve a forward voltage threshold greater than VOUT(CC) at the start-up current. Further details on the diagnostic features in LITIX Basic+ can be found in LITIX Basic+ Diagnostic features

An external temperature derating can be achieved by placing a PTC type resistor at the IN_SET pin. A short trace length (few cm) to place the PTC resistor closer to the LEDs is uncritical. For extended trace length PCB ground shifts and potential disturbance may impact the current regulation accuracy.

As the voltage in the IN_SET pin is kept constant at 1.22V the change of the resistance directly correlates to the change in output current. The customer can select the PTC type resistor based on the required derating curve and nominal output current. Often also a normal fixed resistor is placed in series to the PTC to set a max current when the system is at low temperature. PTC resistors with nonlinear resistance curves allow to achieve a derating only from a certain temperature onwards (e.g. current constant up to 75°C and then derating). See for example EPCOS B5960x B59701.

General recommendation: no additional capacitance should be placed at the IN_SET pin.

When the TLD1114-1EP is used without the MOSFET no PWM dimming over PWMI, EN or IN_SET pin is possible. PWM operation over supply VS is possible as there the current path to the LEDs is disconnected by the switch supplying the module.

The reason is that the LEDs are always connected to the Power Shift resistor without an active switching element to disconnect. Please have a look on the attached figure.

The current path (shown in green) is always closed as there is no switch to open it.

This means even if you deactivate by EN/PWMI or INSET some current is flowing depending on the power shift resistor.

The current can be estimated with IOUT ~(VS - VLED)/(Rpowershift + Rshunt), where

   - Rshunt = 750mOhm if OUTH is used

   - Rshunt = 1500mOhm if OUTL is used.

This means that the only way to turn off the LEDs is to deactivate the power supply (as done e.g. in a fog light).

In case you want to do the wiping animation you will have to use the Power shift feature WITH mosfet.

See TLD1114-1EP Powershift appnote for further details:

https://www.infineon.com/cms/en/product/power/lighting-ics/litix-automotive-led-driver-ic/litix-basic-plus/tld1114-1ep/#!documents

For all LITIX Basic variants with "Open Load" detection functions the following recommendation applies: 

• LITIX Basic ICs with integrated Open Load functions require a capacitive divider on the OUT. This means CVS2OUT and COUT2GND should be implemented to achieve a robust EMC design. This has been evaluated during our EMC investigations. The reason for this is to increase filter capacitance on the OUT. If it is only done via increasing the COUT2GND capacitor, the open load detection is not working properly anymore. To avoid this the CVS2GND has been recommended as well. 

For all LITIX BASIC ICs without the "Open Load" detection function implemented the following recommendation applies: 

• LITIX Basic products without Open Load detection functions such as TLD1120 do can skip the CVS2OUT capacitor.
• The GND connection of the LED load can cause a parasitic behavior during the BCI test. The layout of the PCB Board design is also an important factor how many disturbances the IC OUT or in this case the current regulation loop of the IC will see during the BCI test. The COUT2GND will filter eventual disturbances and ensure a more stable output current regulation. 

NOTE: The actual datasheet drawing of the TLD1120 is showing a CVS2OUT capacitor only! This may not solve BCI issues and a COUT2GND filter is recommended. A dedicated AppNote is planned to focus on this topic.