Version: **

Question: Why am I getting an error trying to program/debug using Visual Studio Code?

Answer: Version 1.4.0 or later of the Cortex-Debug plugin contains changes that are not compatible with launch configurations used for ModusToolbox™ 2.4 applications. To resolve the issue, revert the plugin version to 1.2.2 or earlier.

Click Uninstall > Install Another Version… and then select version 1.2.2 to install.

When the installation completes, click Reload.

Version: **

It is often a requirement for a custom programmer tool to detect any tamperings with the hex file that is to be flashed into a PSoC™ device. In such situations, it is helpful if the programmer software can calculate the checksum of the hex file and compare this value with the checksum at address location 0x90300000 and if both match, then it indicates that the hex file is tamper-free.

The checksum for the hex file generated in ModusToolbox™ can be generated and loaded in address location 0x90300000 by using the python script.

To use the python script, do the following:

1. Extract and copy the ‘hexCheckSumScript.py’ file to the folder containing the hex file, such as ‘mtb-example.hex’, whose checksum is to be calculated.
2. Open a command prompt (Win Key + R and open ‘cmd’)
3. Navigate to the folder containing ‘hexCheckSumScript.py’ and the ‘mtb-example.hex’ using the command “cd <path to folder >”
4. Run the following command to get the checksum of the hex file:

•        python   hexCheckSumScript.py   <Name of hex file>

After the script runs, it generates a new hex file with the prefix “csout_” in the same folder in which the python script and the input hex file are located.

Example operation:

Figure 1  Script execution & output hex file generation                    

Verify if the checksum has been added to the hex file by checking the last three lines of the generated hex file as shown in Figure 2.

The custom programmer software verifies if the hex file has been corrupted/modified by calculating the checksum of the hex file and comparing the same with the hex file value mentioned in the second last line ( 0xD07C as shown in Figure2).

Note:  Python version tested on v3.10.4

Version: **

First-generation TRAVEO™ devices support different security features which can be defined in dedicated BootROM markers in TC-Flash. This article explains these features and how they affect the failure analysis (FA) process.

Infineon offers detailed failure analysis for devices that are suspected to be damaged, show a degradation over time in hardware, or violate the device specification. Check with your regional quality partner for details of how to handle such devices.

During design time of a customer project, the configuration of the security is very important. On the one hand, you should ensure a secured system which is protected against intrusions from attackers. On the other hand, the settings should allow a comprehensive analysis of the device during the FA process. So, there is always a trade-off which the customer has to consider. Contact Infineon support team if you are unsure how the security configuration will affect the FA process during the lifetime of the product.

Note : that any TRAVEO™ T1G MCU family device can be configured in a way to lock the device completely which make it impossible to perform the entire testing the device on the ATE test machine at Infineon because the test mode cannot be enabled. In such cases, the device security must be disabled, by at least erasing the TC-Flash sector SA0.

This article also shows recommended configuration sets for device security.

The markers are evaluated and copied during the boot phase of the device into dedicated registers which can be partially overwritten in some configurations. The BootROM markers are located in the beginning area of Sector 0 (SA0) of the TC-Flash memory.

Overall there are different BootROM marker groups for different purposes.

1) Security Record (SR) register group

Here, security can be enabled and configured. This is the most critical parameter set and must be defined carefully. Some configuration can lock the device completely and there is no back door. Because the device is in that stage, it cannot be recovered. In Security Record registers, the access permissions to TC-Flash (code Flash) and Work Flash also can be defined.

a. Because the MK_SER marker is set to 0x0000 0001, the device security is enabled. The JTAG interface is locked and can only be temporarily opened if a valid device security key (DDR_DSKM0 to DDR_DSKM3) is defined and the Debugger Key Enable Marker (DDR_DSEM) is set to 0x59F71234. The same key must be sent to the target MCU via JTAG. Usually, this is done within a debugger script.If device security is enabled, the next BootRom markers define the behavior of the device.

b. With MK_SSR, the security scope is defined. Note that in Device Protection mode, it is not possible to access the RAM memory in NON-USERMODE. This is important for all operations with the serial programming interface (UART). Usually, a kernel is downloaded into the RAM which communicates with a flash programming tool. In this case, the download of the kernel will fail and only a full chip erase might be possible, depending on the following marker. This marker has no impact to the testability of the device.

c. If the Chip Erase Enable Marker (MK_CEER) is set to a value not equal to 0xFFFF FFFF, chip erase and full chip erase are not possible. This marker has no impact on the testability of the device.

Note that if a misbehavior of the TC-Flash is suspected, the device should not be erased completely to allow a complete flash analysis (e.g., Vt analysis). In this case, only a sector erase of sector SA0 should be performed.

d. The Security Overwrite Enable Marker (MK_SOER) configures the option to overwrite security settings in USERMODE. This could also be possible by a debug session via JTAG. However, the device security key must be known. This marker has no impact on the testability of the device.   

e. The Sector Write Permission Overwrite Enable Marker (MK_SWPOER) is a very critical marker. If Sector SA0 of TC-Flash is write protected, device security cannot be disabled by a sector erase. In this case, set MK_SWPOER to 0xFFFF FFFF. This allows to temporarily disable the write protection of the flash sectors and to erase device security. Keep in mind that this process is possible only if the device security key is known.

It is recommended to set this marker to 0xFFFF FFFF if bit 0 of MK_CSWP0 is set to ‘0’ (write protection of TC-Flash sector SA0).

 
2) Debugger Authentication Record (DDR) register group

Because the device is in protected mode, access through the JTAG interface is locked. It can be temporarily opened by entering a specific Debugger Security Key (also known as JTAG key). The 128-bit key is defined in the debugger Authentication Record along with the Debugger Key Enable Marker. Note that the JTAG interface can be unlocked only if the Debugger Key is enabled and the key itself is a non-trivial key; in other words, it unequal to all bits to ‘0’ or to ‘1’.

Note that the Debugger Key Enable Marker must be set to 0x59F71234 to enable the device security key; otherwise, the JTAG interface cannot be unlocked.

The following BootROM marker settings lock the device completely. Do not use one of these settings when the failure analysis flow is required.

The following are the recommended BootROM marker settings to allow disabling device security with full testability options including detailed analysis of the TC-Flash:

Version: **

When mounting the MCU on the board, connect the exposed pad to the ground. The exposed pad is isolated with an epoxy to the substrate of the die, making it an excellent path to remove heat from the IC. Never connect to other signals.

Note: This KBA applies to the following series of TRAVEO™ T2G MCUs:

• CYT2 series
• CYT3 series
• CYT4 series

Version: **

Refer to the corresponding IDE document for using sin and cos functions in TRAVEO™ T2G CYT2B7. For IAR, refer to EWARM development guide. For GHS, refer to MULTI: Building application for Embedded Arm®.

A sample code for IAR is provided, to show different CPU loading using different option settings.

Standard library math functions for C/C++ are provided by IAR.

There are three different versions; default version, small version, and more accurate version. And, three different variant types are used; double, float, and long double.

The following table shows the sample code and the total time consumed for executing sin, cos, and tan functions for 100 times.

Sample code	Total time consumed for 100 times execution
for (i = 0; i < 100; i++)     {       fresult = __iar_sin_smallf(f_test);       fresult = __iar_cos_smallf(f_test);       fresult = __iar_tan_smallf(f_test);       f_test += 0.01f;     }	Total time = 204us
Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);        for (i = 0; i < 100; i++)     {       fresult = __iar_sin_accuratef(f_test);       fresult = __iar_cos_accuratef(f_test);       fresult = __iar_tan_accuratef(f_test);       f_test += 0.01f;     }	Total time = 384us
Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);        for (i = 0; i < 100; i++)     {       double_result = __iar_sin_small(double_test);       double_result = __iar_cos_small(double_test);       double_result = __iar_tan_small(double_test);       double_test += 0.01f;     }	Total time = 2.62ms
Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);        for (i = 0; i < 100; i++)     {       double_result = __iar_sin_accurate(double_test);       double_result = __iar_cos_accurate(double_test);       double_result = __iar_tan_accurate(double_test);       double_test += 0.01f;     }	Total time = 3.86ms
Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);        for (i = 0; i < 100; i++)     {       long_double_result = __iar_sin_smalll(long_double_test);       long_double_result = __iar_cos_smalll(long_double_test);       long_double_result = __iar_tan_smalll(long_double_test);       long_double_test += 0.01f;     }	Total time = 2.64ms
Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);        for (i = 0; i < 100; i++)     {       long_double_result = __iar_sin_accuratel(long_double_test);       long_double_result = __iar_cos_accuratel(long_double_test);       long_double_result = __iar_tan_accuratel(long_double_test);       long_double_test += 0.01f;        }     Cy_GPIO_Inv(USER_LED_PORT, USER_LED_PIN);	Total time = 3.86ms

Since theTRAVEO™ CY2B7’s CM4 core includes a single precision FPU, for the CPU performance to use float is much better than double and long double variant types. Besides, small and accurate version also has a significant difference in the CPU performance.

Different version can be used based on the application requirement.

Note: This KBA applies to the following series of TRAVEO™ MCUs:

• CYT2B series

Version: **

1. Is the ISENSE pin current limited by both R_CS + opamp input resistance in ICE3PCS01G PFC IC? If yes, what is the value of the opamp internal input resistance highlighted in the attached figure? Explain with an example of 40A allowable start-up inrush current what will be the ISENSE current.
   
   

    

   
   
2. Yes. In the ICE3PCS01G PFC IC, the ISENSE pin current is limited by both R_CS + opamp input resistance. The value of opamp internal input resistance is 7kΩ. This resistor inside the IC that is connected in series with the ISENSE pin is large enough to limit the ISENSE current so that the inrush current during startup will be within the -1 mA – 1 mA range.

See the following example to allow maximum 40A inrush current during start-up.

The selected R_shunt value is 3 mΩ.

The voltage across the R_shunt is V_shunt = IINRUSH × R_shunt = 0.12 V

The current at the ISENSE pin = V_shunt/R_{CS + opamp} = 17 µA, which is within the limit as specified in the datasheet.

3. What are the possible solutions to reduce higher noise in power factor correction (PFC) choke?

Use a capacitor not more than 10nF at the ISENSE pin.

Improve the PCB layout such that the ICOMP capacitor GND does not share any path with another signal, but has a direct path to the IC GND pin.

Infineon resources:

Additional references:

• PFC-CCM (continuous conduction mode) ICs
• Schematic diagram
• EVALPFC2-ICE2PCS03

Version: **

After reset, the debug pins remain in a high-impedance (High-Z) state, and after the boot process, the debug pins are configured as follows:

• TRAVEO™ T2G CYT2 series
• TRAVEO™ T2G CYT3 series
• TRAVEO™ T2G CYT4 series

Version: **

The wait states or cycles is defined as the time between the command input and a stable output. For example, a read command to the DFlash.where the input is the address provided by the CPU and the output is the data provided by the DFlash. The CPU is much faster in the operation than the DFlash, has to wait a certain amount of time (i.e., wait cycles) for the data. To ensure the data correctness and consistency, proper wait states need to be configured in the predefined registers. The right configuration of the wait states or cycles becomes more important in case of a microcontroller operating at high temperature. It is often observed that the short-configured wait states or cycles do not harm under normal or good conditions, but under border conditions this leads to corrupted data, which is later discovered in the field. The following description shows how to calculate the wait states for DFlash of AURIX™ TC3xx device.

The f_FSI value can be derived from the system clock configuration, the usual configuration value is 100 MHz. The other values t_DF and t_DFECC are derivedfrom the datasheet.

Last step is to set the calculated values in the corresponding register.
In the case of using MCAL FLS driver, the wait states or cycles can be configured in the MCAL configuration tool by considering the following two parameters,

FlsWaitStateRead = HF_DWAIT.RFLASH and FlsWaitStateErrorCorrection = HF_DWAIT.ECC.

Note:  This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC3xx series

Version:  **

The TriCore™ architecture supports the closely coupled program and data SRAM memories known as “Program Scratch Pad RAM (PSPR)” and “Data Scratch Pad RAM (DSPR)”.

Following are the local memories implemented by the TriCore™ processor:

• DSPR (RAM, single cycle for local data operations)
• DCache (single cycle for data operations)
• DLMU (RAM, single cycle for local data operations)
• PSPR (single cycle for local code fetch)
• PCache (single cycle for code fetch)
• LPB (multi-cycle flash memory)

The local PSPR and DSPR memories are located in 0xC0000000 and 0xD0000000 respectively. These addresses are called local addresses.

The following table displays the address of the local SRAM memories (PSPR and DSPR) in the global address map.

Table1  Global address map

The global address is used when a CPU access memory via the SRI bus. If a CPU accesses its local PSPR for data operations, for example, data load from 0xC0000000, then it results in a bus transaction with an address in the range from 0x10100000 to 0x701FFFFF depending on the core-ID value of the TriCore™ CPU.

Alternatively, if a CPU accesses its local DSPR for code execution, for example, code fetch from 0xD0000000, then it results in a bus transaction with an address in the range from 0x10000000 to 0x700FFFFF depending on the core-ID value of the TriCore™ CPU.

Note:  The local CPU's global address segment for its DSPR is located in 0x[7 – Core_ID]. For example, if Core_ID is two, then it has its DSPR global address at segment number 0x5.

For more details, see the sub-section “Local and Global Addressing” in the chapter “CPU Subsystem” of the User’s manual.

Note:  This KBA applies to the following series of AURIX^TM MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

The TriCore^TM CPU provides multiple counters to measure various parameters in the CPU without impacting the software execution. The performance counters can be enabled in debugging mode.

The TC1.6.2P CPU, which is used in AURIX™ TC3xx devices, has the following performance counters:

CCTRL SFR is the control register used to enable or disable the counters.

CCNT and ICNT provide the CPU clock and instruction counts respectively.

Additional counters such as M1CNT, M2CNT, and M3CNT can be configured via the CCTRL.M1, CCTRL.M2, and CCTRL.M3 fields respectively. The available counters in TC1.6.2P CPU are as follows:

Using these counters, detailed performance analysis of the executed software can be performed.Insights about various parameters such as the execution time and cache hits or miss can be obtained.. This, in turn, helps to profile and optimize the software.

 Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC3xx series

Version: **

The Auto-discover compiler include paths option enables or disables the scanning of all project folders that detect the include paths needed by the project to compile.
The scanning process occurs every time when a project is built using the Build Active Project or Rebuild Active Project functions as shown in the following figure.

To access this option, right-click an existing project from the C/C++ Projects view and select Properties. Go to AURIX Development Studio > Build. Enable the Auto-discover compiler include paths checkbox by marking it and click Apply and Close as shown in the following figure.

Note: When this function is active it is not possible to manually configure the project include paths anymore.

To add or remove a folder from the compiler include paths when the Auto-discover compiler include paths is disabled, right-click the folder and select C/C++ Compiler Includes > Add Folder as shown in the following figure.

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

This KBA provides the schematic design capture of the CYUSB3KIT-005 EZ-USB™ FX3 camera kit in KiCad. The FX3 symbol file and FX3 camera kit schematic file are attached with this KBA.

KiCad is a free software suite for Electronic Design Automation (EDA). It facilitates the design and simulation of electronic hardware. It features an integrated environment for schematic capture, PCB layout, manufacturing file viewing, SPICE simulation, and engineering calculation.

1 Getting started

1. See Getting started with KiCad for basic information on how to use KiCad for schematic capture.
2. Download the CYUSB3KIT-005 FX3 Camera Kit Base Board.zip file attached with this KBA and extract it to a local folder in your PC.

Once extracted, the following files are available as shown in Figure 1:

• CYUSB3KIT-005 FX3 CAMERA KIT Base Board BOM.xls – BOM
• CYUSB3KIT-005 FX3 CAMERA KIT Base Board Project.zip – Project file archive
• CYUSB3KIT-005 FX3 CAMERA KIT Base Board Schematic.pdf – Schematic
• FX3 Symbol.zip – FX3 symbol file
  

 Figure 1  Extracted folder

 3. Extract the project archive (CYUSB3KIT-005 FX3 CAMERA KIT Base Board Project.zip) to a local folder on your PC.Use the 4. KiCad application to open the KiCad schematic project file (CYUSB3KIT-005 FX3 CAMERA KIT BASE BOARD.kicad_pro) from the extracted folder.

2  Creating EZ-USB™ FX3 design

1. Extract the FX3 Symbol.zip file.
2. Copy the FX3 symbol file (FX3 USB3.0.kicad_sym) from the extracted folder and paste it in the symbol’s library directory (kicad/library/symbols) as shown in Figure 2.

Figure 2  KiCad symbol library directory

3. After adding the FX3 symbol file in the library directory, click Add a symbol in KiCad application (see 1 in the below image) and add the CYUSB3014-BZXI device symbol into the schematic as shown in Figure 3.

4.Similarly, create symbols of all the components used in the design in their respective directories inside the library.

2.1 View the schematic

Figure 4 shows a portion of the FX3 camera kit schematic using KiCad. Open the FX3 Camera kit schematic file using the KiCAD application to view the complete file.

As shown in Figure 5, every component in the schematic should have symbol properties so that all components properties are added to the Bill of Material (BOM).

Figure 5  Symbol properties of FX3 symbol

1.2  Electrical Rule Check (ERC)

a. Annotate the entire schematic before performing ERC as shown in Figure 6.

Figure 7  Performing electrical rules checker

Note : Make sure that all the warnings and errors are resolved.

3  Generating the Bill of Materials (BOM)

1. Click Tools and select Generate BOM as shown in Figure 8.

Figure 8   Generating the BOM

2. Select the appropriate script from the list to generate the BOM as shown in Figure 9.

4 Generating the netlist

1. Click File > Export > Netlist as shown in Figure 12.

Figure 12  Creating Netlist

2. Select KiCad and click Export Netlist as shown in Figure 13.

3. Specify your preferred location as shown in Figure 14.

Version: **

Overview:

In this article, we will discuss the frequently asked questions of the LITIX™ Power TLD6098-1EP and TLD6098-2ES.
TLD6098-x supports Buck, Boost, Buck-Boost, SEPIC (Single-Ended Primary Inductor Converter), and flyback configurations.

1. What are the minimum and maximum values of duty cycles allowed by the TLD6098-1EP and TLD6098-2ES in different modes of operation?

The minimum duty cycle ( )for TLD6098-1EP/TLD6098-2ES is 0 whereas the maximum duty cycle   depends on the switching frequency. The maximum duty cycle in different operating conditions are as follows:

• If the switching frequency is adjusted with an external resistor (adjusted frequency mode), then the maximum duty cycle ( ) is 0.91.
•  If the switching frequency is adjusted with an external clock source in the range of 100kHz to 500kHz (low-frequency sync mode), then the maximum duty cycle ( ) is 0.88.
•  If the switching frequency is adjusted with an external clock source in the range of 2MHz to 2.5MHz (high-frequency sync mode), then the maximum duty cycle ( ) is 0.8.

2. Which parameters should be selected for the constant voltage operation of TLD6098?

For the constant operation range of the device, the voltages on the FBH and FBL pins should be taken into consideration. The FBH and FBL bias currents change depending on whether the sensing is in high or low side mode. If the voltage on the FBH and FBL pins is greater than 2.8 volts, then the sensing is on the high side. However, if the voltage on the FBH and FBL pins is lower than 2.1 volts, then the sensing is on the lower side. To avoid output voltage uncertainty, the voltages of FBH and FBL should be outside the range 2.1 V - 2.8 V.

3. How can I connect the unused pins of TLD6098-2ES?

If not used, PWMO pin (output pin) must be left open. If analog output adjustment is not used, the SET pin has to be connected to IVCC. If the PWM embedded engine is not used, it can be either connected to IVCC or GND, and it depends on the enable strategy adopted.

4. What is the range for the output voltage resistor divider for constant output voltage with TLD6098?

The value of the resistor can be selected as per the requirement and the application. R1 or R3 can be 0 Ohm to reduce the effects of the bias currents. To account for the resistance generated by moisture that may deposit on the PCB over time, the maximum resistance in automotive applications is typically in the 100 kΩ range. If a coating is applied to the PCB, this limitation is not valid any more

5. Is it possible to combine the FPWM/FAULT signals coming from several TLD6098-1EP and TLD6098-2ES into a single FAULT signal? If yes, then how?

Yes, it is possible to combine all the fault signals into a single one. It can be done by connecting a diode network with a common cathode and anode to the respective fault signals. When one of the fault pins is set to high, the common fault signal is also set to high.

6. What is the range of the voltage limit for the SET PIN to grant 100% Vref?

By changing the voltage on the SET pin, the voltage across FBH & FBL pins (Vref) can be varied.

To avoid overvoltage regulation and to achieve the full output current, the voltage on the SET pin should be connected to IVCC pin.

7. Why does the output voltage go above the overvoltage protection threshold?

The voltage may go above the overvoltage protection threshold due to the low resistor value at FPWM PIN/Fault pin. Due to the low resistance value, the device will enter voltage regulation mode. Then the device reacts to over-voltages by raising the voltage of the FPWM/FAULT pin to IVCC. The SWO gate drivers are not getting stopped. Therefore, the output voltage increases further (e.g. in the case of an open load) and the overvoltage occurs.

8. Why is it not advised to put the series resistor in the SWCS pin and how can we avoid the unwanted overcurrent triggering?

The SWCS pin is used as a current sense pin to monitor the voltage on the sensing resistor connected between the switching NMOS source and the ground. As a power ground, it leads the NMOS gate driver's return path. This pin's current is impulsive, with fast transients. TLD6098 has an internal filter that will allow the correct voltage sensing across the RSWCS. During SWO gate driver commutations, a resistor placed between the sensing resistor, RSWCS, and the SWCS pin generates an extra voltage. This extra voltage may cause unwanted overcurrent events, causing the SWO gate driver to be disabled and affecting output accuracy. To avoid triggering unwanted overcurrent events, connect the SWCS pin to the sensing resistor with a low inductance trace that is no longer than 3-4 cm in length. To sense the switching current, a low inductive sensing resistor is also recommended.

Reference: -

1. Datasheet
2. Application Notes
3. Simulation Models

Version: **

For Single Edge Nibble Transmission (SENT) operation Automotive Level (AL) thresholds and 5 V General Purpose Input Output (GPIO) voltage should be used. Then for both falling and rising edges, the PAD switches before reaching the SENT levels, and the thresholds conform with the SENT standard SAE J2716 2010.

Note: This KBA applies to the following series of AURIX MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Translated by: keni_4440091

Original KBA: AURIX™ MCU: How to realize I2S - KBA234446

Version: **

質問： AURIX™ MCUはI2S（Inter-IC Sound）をサポートしますか？

回答： AURIX™ デバイスには、専用のI2S HW-モジュールがありませんが、I2Sマスターおよびスレーブをエミュレートすることができます。

マスター:  AURIX がマスターであるI2S出力を生成するためには、Queued Synchronous Peripheral Interface (QSPI)が使用可能です。それを行うために、QSPIをシンプレックスモード転送モードで使用してください。2つのチップセレクト（SLSO）が必要で、1つは右/左用、2つ目はダミーとしてです。チップセレクトは、BACONエントリを使用して切り替えできます。

スレーブ： スレーブモードでは、AURIX™ は外部マスターからの音声信号を受信します。それを行うには、汎用タイマーモジュール（GTM）のタイマー入力モジュール（TIM）を使用します。例えば、TIM_0は右または左のノイズを検出しています。TIM_1は、クロックをトラッキングし、クロックの立上りエッジでTIM_2をトリガします。次にTIM_2は、データをトラッキングし、Advanced Routing Unit (ARU)を介してFIFOにそれを保存します。FIFOの中で定義された透かしに到達すると、DMAはトリガされ、データがメモリに転送されます。

ユーザーズマニュアルの「Queued Synchronous Peripheral Interface (QSPI)」および汎用タイマーモジュール（GTM）の章を参照してください。

注：このKBAはAURIX MCUの以下のシリーズに適用されます：

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Translated by: keni_4440091

Original KBA: What is XENSIV™ PAS CO2 sensor – Battery Powered Demo Board? - KBA234294

バージョン: **

１．基本データ

「XENSIV™ PAS CO2センサー － バッテリ駆動デモボード」は、完全に機能するボードで、インフィニオンのPASセンサーおよびDPS368圧力センサーの潜在力をデモします。このハードウェアは、ESP32-WROOMおよびカスタムメイドシールドに基づいています。デモボードは、バッテリ駆動で、単一USB接続で充電されます。

2．設定の特徴

2.1　デモボード

• ESP32-WROOM
• バッテリ充電制御
• 3.3V安定化電源用昇降圧コンバーター
• PASセンサー用+12Vステップアップコンバーター
• 1x XENSIV™ PAS CO2センサー
• 1x 圧力/温度センサー（DPS368）
• バッテリ電圧監視

2.2　ブロックダイアグラム

図1　XENSIV™ PAS CO2センサーバッテリ駆動デモボードのブロックダイアグラム

3．設定の写真

3.1  PCB

図2　PASセンサー（上）および圧力センサー（下）のシールドビュー

3.2 PCB 寸法

• 55 mm x 28 mm

4 デモボード詳細説明

4.1 バッテリ充電器

バッテリ充電回路は、テキサスインスツルメンツのBQ24166 ICに基づいています。この回路は、2.5Aで、デュアル入力、シングルセルスイッチモード リチウムイオンバッテリ充電器で、パアーパスマネジメントを備えています。

図3　バッテリ充電器の概略図

図4　バッテリ充電器のシールドビュー 

4.2 昇降圧コンバーター

3.3V安定化のため、バッテリ電圧が3.3Vより大きくても小さくても、TPS63070(Texas Instruments) ICを使用します。この回路は、3.6 Aスイッチ電流を備えた2 Vから16 Vまでの昇降圧コンバーターです。

図5　昇降圧コンバーターの概略図

図6　昇降圧コンバーターのシールドビュー

4.3　ステップアップコンバーター

ステップアップコンバーターは、PAS回路で必要な12Vを生成するために使用されます。

この回路は、アナログデバイス（リニアテクノロジー）のLT3580に基づいており、2Aスイッチ、ソフトスタートおよび同期式の昇圧/反転 DC/DCコンバーターです。

https://community.infineon.com/t5/Knowledge-Base-Articles/Cost-optimized-method-to-generate-12V-and-...

図7　ステップアップコンバーターの概略図

図8　ステップアップコンバーターのシールドビュー

4.4 電池電圧監視

電池電圧の確認のため、TPS3803-01（テキサスインスツルメンツ）ICが使用されます。このICは、簡単な電圧検出です。

回路は、3.4Vよりも低い電池電圧を検出し、uCで読まれるRESETラインをトリガします。

図9　電池電圧検出の概略図

図10　電池電圧監視のシールドビュー

4.5 表示用LED

シールドには4つの異なるLEDが組み込まれています。

• 電池充電（緑色LED）
• パワーグッド表示（外部電源）（緑色LED）
• ヒューマンインターフェース（青色LED）
• ローバッテリー（赤色LED）

4.6 外部電池

充電式電池、CC/CV、3.7V、リチウムポリマー、1.4 Ahがこのプロジェクトで使用されています。

図11　外部電池

5．　使用方法

デモボードセットアップの接続に関して、次の手順に従ってください：

 1．以下の図に示すように、シールドとESP32ボードを一緒に挿してください：

• ESP32のアンテナは、PASセンサーの反対側に付きます。
• PCBを180°回転させないで下さい。

図12　ESP-WROOM-32ボードの向き

2．　以下の図のように、電池をデモボードに接続して下さい：

• 説明
  • 白：　NTCセンサー
  • 黒：　GND
  • 赤：　VDD

図13　外部電池との接続

6　はじめに

センサーとの通信のために、以下のGitHubリンクを確認し、関連するレジスタにプログラムしてキットを使用し始めてください。

インフィニオンのXENSIV™ PAS CO2センサー小型化センサー用C++ライブラリ－

https://github.com/Infineon/pas-co2-sensor

このリンクは、サポートされているフレームワークおよびリファレンスセンサーボードに関して詳細な情報を提供します。

7 関連リンク

ナリッジベース記事

• https://community.infineon.com/t5/Knowledge-Base-Articles/XENSIV-PAS-CO2-sensor-FAQs-KBA234038/ta-p/...

評価ボード

• https://www.infineon.com/cms/en/product/evaluation-boards/eval_pasco2_miniboard
• https://www.infineon.com/cms/en/product/evaluation-boards/eval_pasco2_sensor2go/

リソース

• https://softwaretools.infineon.com/tools/com.ifx.tb.tool.ifxpasco2gui

Translated by: YaNi_3193241

Original KBA: Estimating the power consumption with the XENSIV_PAS_CO2_Power_calculator - KBA234210

ヴァージョン： **

XENSIV_PAS_CO2_Power_calculatorは、XENSIV™PAS CO2センサーを使用して製品を開発するときに、消費電力をすばやく見積もり、電力バジェットに到達するのに役立ちます。

OverviewタブのセルB4に目標消費電力を入力します。 これにより、OverviewタブのセルB5に目標電力を満たすために必要なサンプリングレートが自動的に一覧表示されます。 たとえば、目的のターゲット電力が1 mWの場合、サンプリングレートは210.24秒として計算されます。

逆の計算（特定のサンプリングレートでの消費電力）を実行することもできます。 これを行うには、OverviewタブのセルI9にサンプリングレートを入力します。 次のパラメータの詳細な見積もりを取得します:

1. 3.3Vと12Vの両方の電源を使用する場合のアイドル時間（秒単位）、および電源投入時の測定とアイドリングのパーセンテージとしてのその持続時間。
2. 平均消費電力3.3Vおよび12Vと合計平均消費電力。
3. 12 V電源をオフにしたとき、および3.3V電源と12V電源の両方をオフにしたときの平均消費電力。

Excelシートには、測定頻度が10秒、1分、および1時間ごとの場合の標準電力値も記載されています（上記のリストの項目2および3）。

例については、図1を参照してください。 詳細については、XENSIV_PAS_CO2_Power_calculatorスプレッドシートのHelpタブを参照してください。

図1

Version: **

Garbage collection is an internal process in the FEE (Flash EEPROM Emulation) MCAL (Microcontroller Abstraction Layer) driver. In the FEE MCAL driver for AURIX™ TC2xx and TC3xx, the fill state of the active sector triggers the garbage collection process. During this process, the MCAL FEE driver performs a sector switch and Dflash clean by copying the recent versions of the NVRAM Manager (NvM) blocks to a new sector and erasing the filled sector.

Garbage collection steps:

1. Start the garbage collection process when a write request to a data block crosses the threshold of the active sector.
2. Copy the most recent version of all logical blocks from the active sector to the empty inactive sector.
3. Mark the correct end of the copy procedure by writing a valid state page at the end of the copied data. blocks. The inactive sector becomes the active one. The previous active sector becomes an inactive one.
4. Erase the old sector.
5. Write an erased state page into the erased sector.

Note:  This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

The FlexRay protocol described in the FlexRay protocol specification (irrespective of the version number), is a dual channel protocol (channel A and channel B). Usage of both channels is optional, so it is possible for the FlexRay devices to support a single channel. This may lead to an idea that the channels can be used interchangeably. This flexibility benefits the users in case of severe constraints on pin availability or if there are necessary changes to the PCB design late in the development. This document explains why FlexRay channels cannot be used interchangeably and also provides the recommendation on how to achieve certain level of flexibility in the channel selection.

The following figure shows the block diagram of the FlexRay protocol controller IP module called ERAY. Inside of the ERAY´s kernel there are two dedicated entities; one for channel A and another for channel B. The connection between each channel and the external world through the microcontroller port pins is achieved by using three signals: Transmit Data (TXD), Receive Data (RXD), and Transmit Data Enable Not (TXEN).

In AURIX™ related documentation (for example, User Manual and Datasheet) there is always a suffix added to these signal names to define for which channel these signals are applicable. This implies to the user that these channels cannot be used interchangeable. However, there is a dedicated channel for these signals and their respective port pins.
The reason why the FlexRay channels cannot be interchanged is explained in the FlexRay frame CRC implementation.

FlexRay frame consists of two CRC fields: Header CRC that protects certain header segments and Frame CRC that is computed over header and payload segments. For Frame CRC field calculation, different initialization vectors are used for channel A and channel B defined by the FlexRay protocol specification as follows:

This is the reason why channels cannot be used interchangeably; the transmission of FlexRay frames with the Frame CRC field value calculated for the channel A over channel B (or vice-versa) would lead to the CRC error.

To ease the development of the projects using FlexRay module and to allow greater flexibility in the FlexRay channel selection, AURIX™ devices provide a pin layout where the same pin functionality can be defined for both the channels. For example, AURIX™ TC39x device and the respective datasheet document, we can find the following definition for pin P14.0 (two relevant configurations for this document are marked in the figure below):

This excerpt from the device datasheet can be understood as the pin P14.0 can be used as transmit data (TXD) pin for ERAY module 0, channel A or channel B depending on the pin alternate function configuration. Similar observation can be made for pins P14.1 and P14.9, where P14.1 can be used as receive data (RXD) pin for ERAY module 0, channel A or channel B and P14.9 can be used as transmit data enable not (TXEN) pin for ERAY module 0, channel A or channel B. With these three pins (P14.0, P14.1, and P14.9), the user has complete flexibility in the FlexRay channel selection.

For more details, see the “Pin Definition and Functions” section of the device datasheet document.

Note:  This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series