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Background: In the case of debugging a CM4 application from an .elf file that contains images for both CM0+ and CM4 cores, Ozone by default extracts the SP value from the first vector table it finds, which is usually part of the CM0+ application. As a result, the cores use the same memory area as the stack and the CM0+ core overwrites the contents of the stack to the CM4 core.

Solution: There are two possible solutions.

1. Do not set the SP value in the debug project creation wizard at all. In this case, setting the SP value will be performed by the application that is running on the CM0+ core just before it starts the application on the CM4 core.
   For a newly created project, select the "Do not set" option in the "Initial Stack Pointer" section.
   
   For existing projects, find the _SetupTarget function in the project file and comment out the setting of the initial value of the "SP" register in it.
   

    

2. If the name of the symbol that contains the value of the top of the stack is known, it can be specified in the debug project creation wizard. However, the name of such a symbol depends on the compiler and is often not obvious. For example, for ModusToolbox™ projects compiled with GCC, this symbol is named "__StackTop".
   For a newly created project, select the "Location" option and specify the symbol name in the "Initial Stack Pointer" section.
   
   For existing projects, find the _SetupTarget function in the project file, and then change the way the SP register value is retrieved so that it is retrieved by known symbol's name.
   

    

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The letters U, SV, E, and SE represent the access mode of the register as follows:

For more details, see the Register access modes section in the user’s manual.

• This KBA applies to the following series of AURIX™ MCUs:
• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

VADC (Versatile Analog-to-Digital Converter) is a multi-functionality hardware module that converts analog signals to digital signals with MCU VADC channel pins. See the “Versatile Analog-to-Digital Converter (VADC)” (related to AURIX^™ TC2xx devices) and “Enhanced Versatile Analog-to-Digital Converter (EVADC)” (related to AURIX^™ TC3xx devices) sections of the user’s manual.

DSADC (Delta-Sigma Analog-to-Digital Converter): It is designed specifically to convert the resolver signal sine and cosine information into a digital representation of input angle and velocity. DSADC comes with built-in on-chip carrier generator which produces a selectable output signal (sine, triangle, rectangle) which can be used to simulate resolver signal. Alternatively, you can configure the synchronization of each DSADC input signal to the carrier signal to compensate the error of angle. See the “Delta-Sigma Analog-to-Digital Converter (DSADC)" (related to AURIX TC2xx devices) and “Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC)” (related to AURIX^™ TC3xx devices) sections of the user’s manual.

Note: This KBA applies to the following series of AURIX^™ MCUs

• AURIX^™ TC2xx series
• AURIX^™ TC3xx series

Version: **

To check whether the device supports ISO 11898-1:2015 (ISO CAN-FD) frame format, check the part numbering scheme.

AURIX^™ TC2xx devices

AURIX^™ TC2xx parts that support CAN FD has a special type suffix “N”.

For example, SAK-TC297T-96F300N supports ISO CAN-FD nodes, while SAK-TC297T-96F300S does not.

AURIX^™ TC3xx devices:

All devices that implement CAN module(s) supports ISO CAN-FD nodes.

Note: This KBA applies to the following series of AURIX^™ MCUs

• AURIX^™ TC2xx series
• AURIX^™ TC3xx series

Version: **

The XENSIV_PAS_CO2_Power_calculator helps you quickly estimate the power consumption and arrive at the power budget when developing a product using the XENSIV™ PAS CO₂ sensor.

Enter the Target power consumption in cell B4 of the Overview tab. This automatically list the sampling rate required to meet the target power in cell B5 of the Overview tab. For example, if the desired target power is 1 mW, the sampling rate is calculated as 210.24 s.

You can also do the converse calculation (power consumption for a given sampling rate). To do this, enter the sampling rate in cell I9 of the Overview tab. You get detailed estimates of the following parameters:

1. Idle time in seconds when using both the 3.3-V and 12-V supply, and its duration as a percentage of the power-up measurement and idling.
2. Average power consumption of 3.3 V and 12 V along with the total average power consumption.
3. Average power consumed when the 12-V power supply is turned off, and when both the 3.3-V and the 12-V supplies are turned off.

The Excel sheet also provides standard power numbers when the measurement frequency is every 10 seconds, 1 minute, and 1 hour (items 2 and 3 in the list above).

See Figure 1 for an example. See the Help tab of the XENSIV_PAS_CO2_Power_calculator spreadsheet for more information.

Figure 1

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See the following table:

See the “Standby mode” section of User’s Manual for more information on registers.

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series

Version: **

Question: How to inject faults in PFLASH of AURIX^™ TC2xx MCU?

Answer: To inject faults in PFLASH (Program Flash Memory) follow the below steps:

1. The ECC code causing the required error type (e.g. triple-bit error) can be determined by first programming the data with automatic ECC generation ON.
2. Read this programmed data to find the corresponding ECC code in ECCRPp.RCODE.
3. Switch OFF automatic ECC generation: ECCW.PECENCDIS = 1.
4. Write the value of ECC code (obtained in step 2- in ECCRPp.RCODE) into ECCW.WCODE.
5. Generate the bit errors in the data to program by setting additional bit(s) in the read data.
6. Reprogram the page with this data.

For details, please see the “Program Memory Unit (PMU)” sections of the user’s manual.

Note: This KBA applies to the following series of AURIX^™ MCUs:

• AURIX^™ TC2xx series

Version: **

In general, it allows 2 types of access to the flash in AURIX™ MCU:

• Cached access
• Non-cached access

By using cached access, these improve performance and reduce significantly average access time for memories using cacheable segments.

By default, the program cache is not turned on in the CPU. However, if enable it by configuring PCBYP correctly, and linking your code to the cached area of memory (e.g. 0x80000000 instead of 0xA0000000 for internal flash), then the program cache is enabled.    

See the “Memory Maps (MEMMAP)” section of the User’s manual for more information on registers.

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

For TC26x, TC27x, and TC29x, there are two options (Pull up or Tristate) available, depending on the selection of the HWCFG6 pin (P14.4).

• With HWCFG6 = 1, all port pins except P33.8 and P40.x are set to pull-up mode.
• With HWCFG6 = 0, all port pins except P33.8 and P40.x are set to tristate mode.

Port pins P33.8 and P40.x are in Tristate mode during and after pin activation.

For TC21x, TC22x, and TC23x, all port pins are in Tristate mode during and after pin activation. No HWCFG6 selection is available.

For details on certain dedicated pins reset behavior, please see the “Pull-up/pull-down reset behavior of the pins” sections of the datasheets.

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series

Version: **

Question: Is the AURIX™ MCU support I2S (Inter-IC Sound)?

Answer: The AURIX™ devices do not have a dedicated I2S HW-module, but there are the possibilities to emulate I2S master and slave.

Master: For generating an I2S output, where the AURIX™ is the master the Queued Synchronous Peripheral Interface (QSPI) module can be used. To do so, use the QSPI in simplex mode transmit mode. Need two chip selects (SLSO), one for left/right and the second one as a dummy. The chip-select can be switched using the BACON entries.

Slave: In the slave mode, the AURIX™ is responsible to receive the sound signals from an external master. To do so, the Timer Input Modules (TIM) of the Generic Timer Module (GTM) is used. E.g., TIM_0 is detecting the right or left noise while. TIM_1 is responsible to track the clock and trigger TIM_2 at a rising clock edge. TIM_2 will then track the data and store them through the Advanced Routing Unit (ARU) in the FIFO. By reaching the defined watermark in the FIFO the DMA is triggered to transfer the data to the memory.

See the “Queued Synchronous Peripheral Interface (QSPI)” and “Generic Timer Module (GTM)” sections of the User’s manual.

Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series