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nvSRAMs: Single Event Latch-Up (SEL) & Soft Error Rate (SER)

nvSRAMs: Single Event Latch-Up (SEL) & Soft Error Rate (SER)

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How do Infineon's nvSRAM devices handle SEL and SER events?


Single Event Latch-up (SEL) events in nvSRAMs


Single Event Latch-up (SEL) is a potentially destructive condition involving parasitic circuit elements forming a silicon controlled rectifier (SCR). Normally, this SCR is OFF and only conducting the leakage current. However, if enough voltage (called a threshold voltage) appears across the SCR by a radiation event, the SCR turns ON and conducts current. This current remains until the SCR is completely powered OFF, which is why this condition is called latch-up.

In traditional SEL, the SCR device current may destroy the device if power is not current-limited and removed in time. A removal of power to the device is required in all non-catastrophic SEL conditions in order to recover device operations.

Several mitigation options used for standard latch-up issues can also be applied for SEL issues. The nvSRAM is well protected from SEL events by employing a triple-well architecture underneath the memory core, which creates a low resistive Vcc collection layer for electrons, making it virtually impossible to accumulate enough isolated charge to create a voltage even approaching the threshold voltage required for latch-up.

Infineon has performed both alpha and neutron testing (the main cause of parasitic events in silicon) on our nvSRAMs to measure SEL. All tested samples of nvSRAM on the S8 technology node have successfully demonstrated Zero-SEL events under extreme testing conditions.

Soft Error Rate (SER) events in nvSRAMs


Soft Errors (caused by alpha particles and/or high-energy neutron radiation) refer to random, non-recurring change of state or transient in microelectronic circuits due to energetic nuclear particles interacting with the silicon. Alpha and neutron-induced errors can destroy the integrity of data being stored in SRAM cells, by causing the SRAM latch to flip states. No physical defect is associated with the failing circuit and the device’s normal operation is restored by a simple reset/rewrite operation as opposed to hard fails that cause permanent damage to the device.

However, this could lead to incorrect data being stored in the SRAM memory cell and that will result in a malfunction in the system using the SRAM. These defects are categorized as single bit upset (SBU) if one bit flipped in a byte or multiple bit upset (MBU) if more than one bit flip within a byte. SBU is easier to deal with at the system level, because there are several mitigations and inexpensive algorithms available that can easily correct one bit within a byte.

The Infineon's nvSRAM cell is unique and different from a normal SRAM cell, because it integrates the SRAM and NV memory cell together. Due to the integrated cell architecture, the cell size of nvSRAM is bigger than the standard, 6-transistor SRAM memory bit. The bigger cell size of nvSRAM bit makes it more susceptible to soft errors when compared to normal SRAM cells on the same technology node.

To compensate for this, the nvSRAM memory is architected in such a way that it is virtually impossible to get an MBU, as the bits are spread apart farther than the area caused by the damage from the particle. Therefore, the nvSRAM is capable of producing only single bit upsets. No evidence of multi bit upset (MBU) has been recorded in the nvSRAM in SER testing.

The SER in the nvSRAM has been measured up to a max of only 550 FIT /1 Mb @ 85 ºC. In addition, as mentioned above, single-bit errors can easily be corrected at the system level by implementing appropriate error-correction algorithms. This makes the nvSRAM suitable for all high-reliability applications that are susceptible to SERs. See AN15979 for a description of soft error causes in memories and techniques practiced in nvSRAM to reduce soft errors.


Version: *A

Translation - Japanese: nvSRAMのシングルイベントラッチアップ(SEL)およびソフトエラーレート(SER)- KBA83213 - Community Translated (JA)