Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob

XMC7000 MCU: ADC triggers DMAC when Enable D-cache

lock attach
Attachments are accessible only for community members.

XMC7000 MCU: ADC triggers DMAC when Enable D-cache

LinglingG_46
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 10 questions asked

Question: How to get the ADC result through DMAC when Enable D-cache?

Answer:

  1. When disable the D-cache, the following steps show how to get the ADC result through DMAC.

          1.1 Enable the ADC module in Device Configuration 4.10, choose the DMAC channel which should be used like below screenshot:

LinglingG_46_1-1698025260739.png

1.2Config the DMA channel to achieve the memory copy. Memory copy is an DMAC-specific descriptor type. Memory copy transfer data from the area specified by the source address and size to the destination address.

  • Set DMAC according to the usage example setting.
  • CPU notifies a trigger to DMAC via the trigger multiplexer.
  • DMAC reads the descriptor from the specified area (Descriptor Pointer) when accepting the transfer.
  • DMAC reads the data from the source address (code base address).
  • DMAC writes the read data to the destination address (RAM base address). After that, increment the source address and destination address. DMAC repeats (3) (4) until it reaches the area specified by the transfer size (code size). For example, if we read the ADC result from the register like : “adc_result[0]= (PASS0_SAR0_CH0->RESULT)&0xFFFF”;, in this case, the source address should not be increaed.
  • When memory copy of the specified area is completed, DMAC notifies an interrupt to CPU.

LinglingG_46_2-1698025343944.pngLinglingG_46_3-1698025350042.png

1.3 When the DMA interrupt occurs, the value transferred from ADC result register can be read correctly. The result matches the code design.

2. When enable DCache, the DMA interrupt occurs, but the ram data doesn’t change. The following steps show how to invalidate the cache related with the DMA.

  • Chean D-cache for buffer area. The data of the shared memory match cache memory.
  • Clean D-cache for descriptor area to ensure descriptor data is cleaned out to DRAM, so that it can be accessed by DMA later on.
  • Invalidate D-cache for dstBuffer area. Subsequent access is cache miss.LinglingG_46_4-1698025455112.png

     

3. Reference Manual:

 

Attachments
0 Likes
106 Views
Contributors