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Volatile Register Read latency handling for SEMPER™ NOR flash – KBA235137

Volatile Register Read latency handling for SEMPER™ NOR flash – KBA235137

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Community Translation: SEMPER™ NOR フラッシュの不揮発性レジスタ読出しレイテンシ処理 – KBA235137

Version: ** 

Problem: The HL-T / HS-T flash family requires 1 or 2 latency cycles for volatile register read in 1S-1S-1S mode at >50 MHz, while some of the serial flash host controllers or drivers only support byte-wise ('multiple of 8') latency cycles.

Solution: Read two consecutive bytes and reconstruct the register value.

The SEMPER NOR flash (and other legacy serial NOR flash devices) can output multiple bytes in one Register Read operation. For example, in Read Status Register (05h) operation, the flash continues to output status while CS# is low and clock cycles are provided. If the SEMPER NOR flash is configured as 2 latency cycles for volatile register read
(CFR3x[7:6] = 11b) and the host controller intends to read two status bytes with 0 latency, the host read buffer will be filled with shifted status register values as shown in the following table:

 

Command input (05h)

Latency

Status output (03h)

Partial status output

IO0 (SI)

0

0

0

0

0

1

0

1

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

IO1 (SO)

x

x

x

x

x

x

x

x

x

x

0

0

0

0

0

0

1

1

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

                Buffer[0]

Buffer[1]

 

Follow these settings to reconstruct the status byte from the 2-byte buffer:

Latency = 2;

Status = (Buffer[0] << Latency) | (Buffer[1] >> (8 – Latency));

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