What use cases disable Automatic ECC on the Mirrorbit 65nm Flash family?
Cypress 65-nm MirrorBit NOR Flash designs have an automatic ECC feature that corrects every rare bit errors before the data leaves the flash. The ECC logic uses an Enhanced Hamming Code algorithm that can correct a single bit error per ECC Page. The ECC Page is 16 bytes of user data in SPI NOR devices and 32 bytes of user data in Parallel NOR devices. Each ECC Page of user data is associated with hidden ECC parity bits that are written when the user data is programmed. So long as the ECC parity bits are valid for any given ECC Page, the ECC logic is enabled for read accesses to that ECC Page. Once the ECC parity bits become invalid (see below), then a hidden non-volatile bit is programmed for that ECC Page that disables the ECC logic for all subsequent reads to that ECC Page, until the sector containing this ECC Page is erased.
The hidden ECC parity is computed based on the pattern of 1’s and 0’s that will be in the ECC Page after the programming operation completes. For the first write to an ECC page after the sector has been erased:
If two or more writes are performed on this page, then if:
So, while ECC may not be disabled on an ECC Page immediately upon the second write to that page, it is best to presume that ECC is always disabled after the second write.
If your goal is to maximize the value of the internal ECC feature for your application, see the following application notes: