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Typical handling of VCC and VIO on Flash memory products – KBA236540

Typical handling of VCC and VIO on Flash memory products – KBA236540

Infineon_Team
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Community Translation: フラッシュメモリ製品におけるVCCとVIOの代表的な取り扱いについて - KBA236540

Version: **

Infineon’s serial NOR and parallel NOR flash memory products have two versatile I/O (VIO) power options:

  1. VCC and VIO (may have identical or different voltage levels)
  2. VIO = VCC

Versatile I/O (VIO): The maximum voltage levels accepted at the inputs, and voltage levels driven by the outputs, of a flash device are determined by the specific voltage applied to VIO.  This VIO feature allows the flash device to tolerate input voltage levels from other devices, as well as output voltage levels on the same bus having different voltage interface signal levels, different from that of the device core (VCC) voltage.  The implementation of the VIO feature is not a configuration register setting, but rather a hardware implementation. Therefore, when a specific VIO voltage is applied to the VIO input pin, it sets the I/O voltage levels, different than that of the core VCC, and the I/O pins cannot operate greater than the VIO voltage. 

This knowledge base article will focus on feature options (a) and (b) listed above. Therefore, the user must select the appropriate ordering model number which supports the specific VIO feature option (refer to the respective datasheets for details)..

Solution:

Quad SPI with VCC and VIO feature (‘option a’):

It is recommended that connections of both VIO and VCC should also include 0.1-µF decoupling capacitors.  The decoupling capacitors should be placed as close as possible to the package between the VCC supply input pin and GND, as well as between the VIO supply input pin and GND. The VIO feature is not available for all Quad SPI package options. VIO may be tied to VCC so that interface signals operate at the same voltage as the core VCC of the device. During the rise of the power supplies, the VIO supply voltage must remain less than or equal to the VCC supply voltage. For a backward compatibilty with the SO16 package, the VIO supply is tied to VCC inside the package, and the I/O pins will function at VCC level. Therefore, when VIO = VCC, the VIO supply is tied to VCC internal to the package. The block diagram applies to the Quad SPI packages with separate VCC and VIO input pin connections, requiring different circuit voltage requirements. Refer to AN98058 - “Serial Peripheral Interface (SPI) FL Flash Layout Guide” for additional design layout details and specifications.

Infineon_Team_2-1669022542324.png

QSPI voltage levels:

FS-S:      VCC = 1.7V - 2.0V

                VIO = no option

FL-S:      VCC = 2.7V - 3.6V

                VIO = 1.65V - 3.6V

Parallel NOR with VCC and VIO feature (‘option a’):

Similar to that of the Quad SPI connections, it is recommended that connections of both VIO and VCC should include 0.1-µF decoupling capacitors. The decoupling capacitors should be placed as close as possible to the package between the VCC supply input pin and GND, as well as between the VIO supply input pin and GND.  During the rise of the power supplies, the VIO supply voltage must remain less than or equal to the VCC supply voltage. The block diagram applies to NOR packages with separate VCC and VIO input pin connections, requiring different circuit voltage requirements. Refer to AN216200 - Non-burst-mode parallel NOR flash memory - layout guide for PCBs” for additional design layout details and specifications.

Note:  The BYTE# input signal is tied to VIH to depict x16 (WORD) mode (DQ0 through DQ15) data width.

Infineon_Team_1-1669022480844.png

 

PNOR voltage levels:

GL-T, GL-S:         

VCC = 2.7V - 3.6V
VIO = 1.65V - 3.6V

Infineon_Team_0-1669022441846.png

 

Parallel NOR with VIO = VCC feature (‘option b’):

For VIO = VCC models, the VIO input signal pin is tied externally to VCC so that interface signals operate at the same voltage as the core VCC of the device. During the rise of the power supplies, the VIO supply voltage must remain less than or equal to the VCC supply voltage.  The VIO input signal pin cannot be left floating or connected to GND.  Therefore, externally connecting VIO directly to VCC is required, and the I/O pins will function at VCC level.

Note:  The BYTE# input signal is tied to VIH to depict x16 (WORD) mode (DQ0 through DQ15) data width.

PNOR voltage levels:

GL-T, GL-S:         

VCC = 2.7V - 3.6V
VIO = 2.7V - 3.6V

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