The clock source of basic watchdog timer is ILO0. MCWDTs are clocked by LFCLK. ILO0, ILO1, WCO, or ECO can be configured as a clock source of LFCLK.
For basic watchdog, a RESET is triggered if the watchdog is not serviced before the upper limit. In the window mode, a RESET is triggered if the servicing occurs before the lower limit is reached.
For MCWDTs, the RESET trigger mode is different from basic WDT.
When the counter reaches MCWDTx_CTRy_UPPER_LIMIT, a FAULT is issued. If the firmware does not handle this FAULT to bring the system back into a safe state, a RESET is issued after a fixed number of LFCLK cycles.
Counter is serviced before MCWDTx_CTRy_LOWER_LIMIT is reached: The counter is serviced too early; a FAULT is issued followed by a RESET if the FAULT is not handled in time by the firmware.
Basic WDT will be enabled after power-on. WDT_CTL is enabled, by default. After power-on, WDT will count automatically. When ENABLE bit of WDT_CTL changes from 1->0, the counter is cleared.
MCWDTs will not be enabled after power-on automatically. The MCWDT counters are enabled by setting the ENABLE bit in the MCWDTx_CTRy_CTL and MCWDTx_CTR2_CTL registers and are disabled by clearing it.