No, IMO bit must be enabled at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES.
This bit would be automatically set by the hardware when there is a reset and the time taken by hardware to set this bit will mostly fall under the boot time (ROM boot + Flash boot) itself. After this, the bit is not expected to become 0 and this bit shall always remain 1 during normal operation.
Some of the registers are retained in DeepSleep while the others are not. To find if the register is retained, see the device-specific Registers TRM.
Debug pins are configured to specific drive modes in BOOT (see section "32.5 Pin Configuration of Debug Interface on BootROM" in Traveo™ II Automotive Body Controller Entry Family Architecture Technical Reference Manual (TRM). . These pins need to be set to High-Z in the application before entering DeepSleep to avoid an increase in current consumption due to these drive modes.
If the intent is to put the device into DeepSleep mode, all cores will have to be put into DeepSleep modes independently. Each core can enter DeepSleep regardless of the others.
On attempting to put any core into DeepSleep, the device enters Deep-sleep mode when all cores are in DeepSleep and when PWR_CTL.LPM_READY is 1. Before transitioning to DeepSleep clock sources should be changed from ECO (if used) to IMO. For transitions states, see the Power mode transition table in the Architecture TRM.
The DeepSleep regulator is used to power CLK_LF modules (ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration memories such as Retention registers, Cache tag structures, Cache least recently used (LRU) structures, Cache data structures) in DeepSleep mode, and then the reference clock for the CLK_LF domain can be enabled or selected from ILO0, ILO1, or WCO.
The WIC (wake up interrupt controller) provides detection of DeepSleep interrupts in the DeepSleep power mode. After wakeup, the device enters the previous power mode that the core operated in and the clocks are enabled or restored by hardware.
Each CPU has independent WIC settings, and the interrupts capable of waking up the individual CPUs are configurable and independent of the other. Hence, CM0+ need not be kept in Active mode for clocking CM4.