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Traveo II Automotive Body Controller - FAQ – CPU - KBA232509

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Traveo II Automotive Body Controller - FAQ – CPU - KBA232509

Home Page: Traveo II Automotive Body Controller - FAQ – CDC -... - Cypress Developer Community

7. CPU

 

7.1.  Is there a way to prevent the program execution from an unused region of memory?

If you want to avoid execution from a specific region of the memory (like the unused CodeFlash), you can configure the Memory Protection Unit (MPU) to not execute from this region. If the program tries to execute from this region, Memory Management Fault Exception will be triggered. For more details on MPU, see the Arm User Guide.

7.2. Do Traveo II Body High devices support exclusive memory instructions?

No, CM7 in the Traveo II Body High devices do not support exclusive memory access instructions. If you are trying to implement semaphore, you can use the IPC resource available in Traveo II.

7.3. I am unable to write to the M7 CPU registers like VTOR and TCM-related registers. What could be the reason?

CPUSS_CM7_x_CTL.PPB_LOCK is used to control the write to these registers. These bit fields should be 0 to enable writing to these registers. For details, see the Registers TRM.

7.4. What is the purpose of CPUSS_CM0_PC_CTL and CPUSS_CM0_PCx_HANDLER registers?

CPUSS_CM0_PC_CTL and CPUSS_CM0_PCx_HANDLER registers are protected by PERI_MS_PPU_FX_CPUSS_BOOT PPU and cannot be modified. These registers are intended to be used by the boot code. Currently, only the CPUSS_CM0_PC1_HANDLER is used for the system call in the following way. When the exception handler address matches CPUSS_CM0_PC1_HANDLER, PC is changed to '1',which is required to execute system call. So, these registers cannot be used in for user application.

7.5. What is the status of the CM4/7 cores after the boot process?

After the reset, the CM4/7cores will be in DeepSleep until they get enabled by CM0+.

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