For the mapping of the group and slave for the peripheral, see the ‘Peripheral I/O Map’ section in the device datasheet.
Example: In CYT2B7 devices, the SCB belongs to group 6 with seven slaves, so PERI_GR6_CLOCK_CTL will be used to set the divider and PERI_GR6_SL_CTL will be used to enable/disable the slave clock gate.
It takes four cycles of the originally selected clock to switch away from it and the original clock should not be disabled during this time.
On start up or boot the default clock is the IMO. ECO can be configured as the clock source later in the application code. Regardless of whether ECO is set as the clock source later, cm0+ applies the ECO trims during the boot up process along with other regulator trim values.
Under ideal conditions when the ECO is configured as the clock source in the application code, it would be set as the clock source after its amplitude has stabilized. If ECO is not populated, the amplitude stabilization timeout occurs, the ECO_OK and ECO_READY would fail and the application code would be stuck in a while loop.
while(SRSS->unCLK_ECO_STATUS.stcField.u1ECO_OK == 0ul);
while(SRSS->unCLK_ECO_STATUS.stcField.u1ECO_READY == 0ul);
If the above fields fail, there is no ‘fall back’ mechanism that would allow the MCU to continue operation using IMO.
Ideally, all HF paths (CLK_HFx) can be configured to derive their source from any PLL clock path (CLK_PATHx). There are no limitations. However, multiple clock paths enable you to scale the frequency required for the operation of specific IPs shown in Table 46 (clock specifications) of the datasheet. With all CLK_HFx deriving clock from a single clock path, the Pre-dividers of each HF path would be able to provide certain limited frequencies and lose out on scalability.