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Traveo II Automotive Body Controller - FAQ – ADC- KBA232509


Traveo II Automotive Body Controller - FAQ – ADC- KBA232509

Home Page: Traveo II Automotive Body Controller - FAQ – CDC -... - Cypress Developer Community

4. ADC


4.1. What is the use of analog calibration in ADC? How is it performed?

Analog calibration is used to make the actual ADC transfer curve come closer to the ideal transfer curve. Analog calibration can correct an offset and gain error. Before the ADC is used for acquisitions, it must be set to the correct values (e.g., periodic calibration of the production line due to temperature shift and age). The following figure shows the deviation in the actual transfer curve from the ideal curve during an ADC operation.


The ideal transfer curve has the following characteristics:

  • Transition between values 0x000 and 0x001 for VREFL + 0.5 LSB input voltage. 
  • Transition between values 0xFFE and 0xFFF for VREFH – 1.5 LSB input voltage.

If this is not the case, the ADC is needed to be calibrated. The ADC calibration takes place in two parts: 

  • Offset Adjustment
  • Gain Adjustment

Analog calibration is controlled by the configuration register PASSx_SARy_ANA_CAL, which contains an 8-bit analog offset (PASSx_SARy_ANA_CAL.AOFFSET) and 5-bit analog gain (PASSx_SARy_ANA_CAL.AGAIN) calibration values. Before the ADC is used for acquisitions, these values need to be set to the correct values; that is, the ADC needs to be calibrated.

See AN219755 – Using a SAR ADC in Traveo II Family  for the detailed procedure of Offset Adjustment (Section 9.4) and Gain Adjustment (Section 9.5).

4.2. What is ADC pre-conditioning? Where is it used?

The Traveo II SAR ADC has a “pre-conditioning” feature in which the ADC sample capacitor can be charged or discharged before sampling the input signal. The use of this feature is optional and is defined by the PASSx_SARy_CHz_SAMPLE_CTL.PRECOND_MODE field of channel configuration. There are four possible selections:

  • OFF – no preconditioning
  • VREFL – discharge to VREFL
  • VREFH – charge to VREFH
  • DIAG – connect to the diagnostic reference output during preconditioning

The following are the two use cases:

  • The preconditioning feature is used in broken wire detection such as “open”, “short to ground”, and “short to 5V”.  The ADC channel is preconditioned by charging the sampling capacitor to VREFH and measuring the ADC count. The channel is then preconditioned by discharging the sampling capacitor to VREFL and measuring the ADC count again. Now, the following cases can arise:
  • The conversion result will stay at an almost 5-V constant value after charging and at almost 0-V constant value after discharging. This means that there is an “open” fault.
  • The conversion result will go to 0 V immediately after charging and will stay at 0 V value after discharging. This means that there is a “short to ground” fault.
  • The conversion result will stay at almost 5-V constant value after charging but will immediately go to 5-V value after discharging. This means that there is a “short to 5V” fault.

If none of the above occurs, you can assume that there is no broken wire fault in the channel.

  • Another use case is reducing the sample time for the channel. There may be cases when the input voltage on multiple channels is around a fixed voltage (say 2.5 V). Therefore, with pre-conditioning to a known reference voltage (2.5 V here), the time taken to charge the sampling capacitor to the input voltage can be reduced; this means that the sampling time can be reduced.
4.3. As per the datasheet, up to 32 analog pins can be connected to the SARMUX inputs. Can I connect more external inputs to the same ADC?

Yes, you can expand the number of analog inputs beyond the available input pins.

The SARMUX supports the use of an external mux, which can be used to achieve this feature.  Each channel configuration has its own 3-bit-wide external mux select value (see the PASSx_SARy_CHz_SAMPLE_CTL.EXT_MUX_SEL register field for select values). This allows up to eight channels to use the same analog input pin with different select values. The per-channel external mux enable bit (PASSx_SARy_CHz_SAMPLE_CTL.EXT_MUX_EN) can be used as a chip select for the external mux select device.

4.4. How do we configure the sample time for the ADC channel? What is the appropriate value for the sample time?

The sample time is the time in which the sampling capacitor of the sample-and-hold circuit of the ADC charges to the input voltage level.

In this SAR ADC, each channel configuration has its own sample time definition (PASSx_SARy_CHz_SAMPLE_CTL.SAMPLE_TIME). This time needs to be translated to the number of SAR clock cycles. PASSx_SARy_CHz_SAMPLE_CTL.SAMPLE_TIME is a 12-bit field and the legal values are [1….4095] (‘0’ will be interpreted as ‘1’). The recommended minimum sampling time required for proper charging of the sampling capacitor to the channel input voltage level is given in the respective device datasheet (e.g., 412 ns for the TVII-BE-1M device). The maximum clock frequency for the SAR ADC is 26.7 MHz (80/3 MHz) to achieve the 1 Msps throughput, so the recommended sample time corresponds to ~11 clock cycles at this frequency.

The sampling time should be set such that it gives enough time for the sampling capacitor to properly charge. Another factor to consider is that setting a very high sampling time will also introduce delay and slow down the overall ADC operation. To get the appropriate value of the sample time, consider the ADC equivalent circuit for an analog input as shown below:


Here, we have:

REXT: Source impedance, CEXT: On-PCB capacitance, CIN: I/O pad or Input capacitance, RVIN: ADC equivalent input resistance, CVIN: ADC equivalent input capacitance, K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))

Sampling Time (tSAMPLE) requirement is shown in the following equation:

tSAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]

K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at12-bit resolution (LSbSAMPLE = ±0.5). See the device datasheet for the exact value of internal parameters.

4.5.  What is the ADC channel group?

An ADC channel group is a group of channels which can be triggered using the same trigger. A group can only contain sequential channels and cannot have overlapping groups or group within a group. The number of channels in a group can be anywhere from one (single channel) to 32. Separate groups can have different number of channels.

Consider the following while making an ADC channel group:

  • The first channel, which defines the trigger in the group must be enabled.
  • The last channel, which defines the end in the group must be enabled.
  • A channel in the group may be disabled; if disabled, it will be skipped.
  • A group implicitly ends at the last existing and enabled channel.
4.6. What is ADC trigger? What are different trigger options for the SAR ADC in Traveo II?

An ADC trigger is used to start the acquisition and conversion of the of the input signal. The ADC trigger for a group will execute the acquisition as defined by configurations of the channel in the group. The trigger for a channel group is selected by the configuration (PASSx_SARy_CHz_TR_CTL.SEL) of the first channel of the group. There are seven possible hardware and software trigger options:

  • TCPWM – one-to-one trigger output from a corresponding TCPWM
  • GENERIC0-4 – five generic input triggers routed to this ADC
  • CONTINUOUS – this trigger is always HIGH, making the group always triggered; or in other words, Idle trigger
  • OFF – no hardware trigger

A group can be software-triggered by setting the PASSx_SARy_CHz_TR_CMD.START bit. This software trigger can be used even if the group is configured to use a hardware trigger.

4.7. What are VREFH and VREFL?

VREFH and VREFL are the high voltage reference and low voltage reference for the internal DAC of the SAR ADC, respectively. It is the reference pair for all SAR ADC blocks present and supplied externally from the dedicated pin of input pins (VREFH and VREFL). For the 12-bit SAR ADC, the input voltage of value VREFH would correspond to the digital output of 0x0FFF and the input voltage of value VREFL would correspond to the digital output of 0x0000. Hence, all the input must lie in the range of VREFL to VREFH. The ADC input reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA.

4.8. Is it possible to use a voltage that is or is derived from the 0.9 V band gap voltage as reference voltage for an AD conversion?

No, it is not possible to bypass the VREFH and use an internal bandgap of 0.9 V instead of VREFH. The reference voltage for the SARADC is directly supplied externally from the dedicated pins (VREFH and VREFL). There are no register settings to bypass it.

4.9. After PASSx_SARy_CHz_TR_CMD.START is set, ADC conversion stopped. What could be the reason?

The possible reason could be that the interrupt, PASSx_SARy_CHz_INTR.GRP_CANCELLED, is set and the conversion  stopped. By default, PASSx_SARy_CHz_TR_CTL.PREEMPT_TYPE is set as ABORT_CANCEL (0x00). In this case, if an acquisition is aborted, it will neither return Clear pending trigger for aborted group nor set Cancelled interrupt. Change PASSx_SARy_CHz_TR_CTL.PREEMPT_TYPE to other values could solve the issue.

4.10. Does SAR ADC in Traveo II support self-diagnostic feature, that is, does it contain any diagnostic register which is set when there is any short or open circuit fault?

No, the SAR ADC does not contain any self-test register. But, these test mechanisms can be implemented in the software using other available ADC features. For example, Short and Open circuit fault can be detected using ADC preconditioning feature, as described in Q4.2 of this document. For further details, see the Architecture TRM.

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