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The edge selection for LVD in TRAVEO™ T2G MCU

The edge selection for LVD in TRAVEO™ T2G MCU

arakawa
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This KBA explains the edge selection for LVD in TRAVEO™ T2G MCU.

Japanese Translation: TRAVEO™ T2G MCUにおけるLVDのエッジ選択

The LVD detects a low voltage or a high voltage by the action trigger set by the edge selection. (setting HVLVD1/2_EDGE_SEL bit in PWR_LVD_CTL/2 register). The edge selection is for selecting which edges will trigger action from the output of the comparator implemented on the LVD.

The following explains which edge should be selected for the behavior of VDDD voltage.

  1. If VDDD voltage falls, and VDDD voltage crosses the configured threshold voltage:

In this case, the comparator output changes from High to Low. Therefore, setting HVLVD1/2_EDGE_SEL bit to "0x2: FALLING" or "0x3: BOTH" cause the LVD to detect a low voltage for VDDD.

  1. If VDDD voltage rises, and VDDD voltage crosses the configured threshold voltage:

In this case, the comparator output changes from Low to High. Therefore, setting HVLVD1/2_EDGE_SEL bit to "0x1: RISING" or "0x3: BOTH" cause the LVD to detect a high voltage for VDDD.

More information

  • TRAVEO™ T2G Architecture TRM
  • TRAVEO™ T2G Register TRM

 

Note:

This KBA applies to the following series of TRAVEO™ T2G MCUs:

  • TRAVEO™ T2G CYT2xx series
  • TRAVEO™ T2G CYT3xx series
  • TRAVEO™ T2G CYT4xx series
  • TRAVEO™ T2G CYT6xx series
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