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TRAVEO™ T2G MCU: JTAG pin configuration after reset and how to avoid undesired consumption current in DeepSleep mode

TRAVEO™ T2G MCU: JTAG pin configuration after reset and how to avoid undesired consumption current in DeepSleep mode

Niimi
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This KBA explains JTAG pin configuration after reset and how to avoid undesired consumption current in DeepSleep mode in TRAVEO™ T2G MCU.

TRAVEO T2G supports JTAG and SWD protocol. By default, the JTAG mode is selected on a power-up reset and the JTAG protocol can be used.

After reset, JTAG pin are configured as below during boot process.

Pin Name

Input Enable

Drive Mode

swj_trstn

Yes

Internal Pull-up

swj_swo_tdo

Yes

Strong(output)

swj_swdoe_tdi

Yes

Internal Pull-up

swj_swdio_tms

Yes

Internal Pull-up

swj_wsclk_tclk

Yes

Internal Pull-down

 

“swj_swo_tdo” pin is configured as input enabled and Strong output. According to DAP specification, output of this pin is high-z while DAP is idle.

This might result in leak current from “swj_swo_tdo” pin power source, e.g. VDDD in CYT2xx series, though input buffer. Please re-configure input buffer of this pin from enabled to disabled to avoid unwanted power consumption in low power mode, especially DeepSleep mode.

e.g. relating register of CYT2B9:

GPIO_PRT23_CFG.IN_EN4 = 0u // input buffer disable

More information

  • TRAVEO™ T2G Architecture TRM
  • TRAVEO™ T2G Register TRM
  • TRAVEO™ T2G Application Note

Note:


This KBA applies to the following series of TRAVEO™ T2G MCUs:

  • TRAVEO™ T2G CYT2xx series
  • TRAVEO™ T2G CYT3xx series
  • TRAVEO™ T2G CYT4xx series
  • TRAVEO™ T2G CYT6xx series
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