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TRAVEO™ T2G MCU: Flash Program/Erase Protection by SMPU and SWPU

TRAVEO™ T2G MCU: Flash Program/Erase Protection by SMPU and SWPU

QuangPhamMinh
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When a master calls SROM APIs to program or erase Code/Work Flash, master’s access permission to the related memory regions will be evaluated by the SROM API based on SMPU and SWPU protection configuration.

Saying “M” is the master that requests SROM API to erase or program a Code/Work Flash memory region, SROM API refers to SMPU protection settings to determine if ”M” has access permission to the source region and refers to SWPU protection settings to determine if “M” has permission to program or erase the target region.

Here, source region means the memory region holding the source data to be loaded for write operation while target region is the memory region to be written or erased.

The following table shows how SMPU and FWPU protection settings take part in evaluating master M’s access permission.

Table 1: Effect of SMPU and FWPU on Flash erase/program SROM APIs

QuangPhamMinh_3-1696326835439.png

×: Protection configurations do not involve in evaluating master’s access permission

〇: Protection configurations involve in evaluating master’s access permission

‐:No relevant configuration

※1) Status code return 0xF000_0005 if the master that requested System Call doesn't have access(write/secure access) permission to the target region.

※2) Status code return 0xF000_0008 if the master that requested System Call doesn't have access(read/ secure access) permission to the source region.

More information

  • TRAVEO™ T2G Architecture TRM
  • TRAVEO™ T2G Register TRM

Note:

This KBA applies to the following series of TRAVEO™ T2G MCUs:

  • TRAVEO™ T2G CYT2xx series
  • TRAVEO™ T2G CYT3xx series
  • TRAVEO™ T2G CYT4xx series
  • TRAVEO™ T2G CYT6xx series
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