Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

TRAVEO™ T2G MCU: CRC calculations by P-DMA - KBA236012

TRAVEO™ T2G MCU: CRC calculations by P-DMA - KBA236012

BinduPriya_G
Community Manager
Community Manager 250 replies posted First like received 50 sign-ins
Community Manager

TRAVEO™ T2G MCU: CRC calculations by P-DMA - KBA236012

Version: **

In addition to DMA descriptors for Single, 1D and 2D transfers the Peripheral DMA (P-DMA) in TRAVEO™ T2G also supports a Cyclic Redundancy Code (CRC) transfer descriptor type.

Following hints and considerations may be helpful when using this descriptor type:

Post-processing of CRC result

CRC standards define the following post-processing operations that must be applied to the result of a CRC calculation:

  • A value that must be XOR’ed with the result (DWx_CRC_REM_CTL0)
  • Whether the bit order of the result (after XOR) must be reversed or not (DWx_CRC_CTL0. REM_REVERSE)

The post-processed result of a completed P-DMA CRC calculation is only available in the DWx_CRC_REM_RESULT0 register, where the configured destination address (DST_ADDR) of the CRC transfer will only hold the result without post-processing (matching DWx_CRC_LFSR_CTL0).

By using the feature of DMA descriptor chaining, it is possible to transfer the post-processed result to the desired target memory as well. This may be useful when the CRC result shall be appended to the memory buffer that holds the data for which the CRC had been calculated (for example, before transmitting it over SPI).

Consider the following three common scenarios:

1.CRC length is 32-bit.

A descriptor for a Single transfer can be chained with the following parameters:

  • DATA_SIZE:                                 32-bit
  • SRC_TRANSFER_SIZE:            DATA_SIZE (or 32-bit)
  • DST_TRANSFER_SIZE:            DATA_SIZE (or 32-bit)
  • SRC_ADDR:                                 DWx_CRC_REM_RESULT0
  • DST_ADDR:                                  Desired target address, 32-bit aligned

2. CRC length is 8-bit or 16-bit and DWx_CRC_CTL0. REM_REVERSE == 0 (no bit reversal)

A descriptor for a Single transfer can be chained with the following parameters:

  • DATA_SIZE:                                 8-bit or 16-bit as required
  • SRC_TRANSFER_SIZE:            32-bit (register needs to be accessed with 32-bit width!)
  • DST_TRANSFER_SIZE:            DATA_SIZE
  • SRC_ADDR:                                 DWx_CRC_REM_RESULT0
  • DST_ADDR:                                  Desired target address, aligned to DATA_SIZE

3.CRC length is 8-bit or 16-bit and DWx_CRC_CTL0. REM_REVERSE == 1 (bit reversal)

Due to the bit reversal, the relevant result value is stored in the most significant byte(s) of DWx_CRC_REM_RESULT0. This register can be only accessed with 32-bit and the type casting via DATA_SIZE would only operate on the least significant byte(s). Therefore, an intermediate step is necessary that copies the DWx_CRC_REM_RESULT0 value somewhere to SRAM, because the SRAM would then allow arbitrary access width in the second step.
This means two descriptors for Single transfers should be chained with the following parameters:

  • Descriptor #1 (copy value from register to temporary SRAM location)
    • DATA_SIZE:                        32-bit
    • SRC_TRANSFER_SIZE:  DATA_SIZE (or 32-bit)
    • DST_TRANSFER_SIZE:  DATA_SIZE (or 32-bit)
    • SRC_ADDR:                        DWx_CRC_REM_RESULT0
    • DST_ADDR:                        Temporary address X in SRAM, 32-bit aligned
  • Descriptor #2 (extract relevant bytes from temporary SRAM location and copy to target address)
    • DATA_SIZE:                        8-bit or 16-bit as required
    • SRC_TRANSFER_SIZE:  DATA_SIZE
    • DST_TRANSFER_SIZE:  DATA_SIZE
    • SRC_ADDR:                        X+2 for 16-bit, or X+3 for 8-bit
    • DST_ADDR:                        Desired target address, aligned to DATA_SIZE

Additional notes:

  • CRC standards with a CRC length not equal to 8, 16, or 32 bits need some extra steps which could also require the CPU (for example, for bit shifting)
  • A sophisticated DMA descriptor chain to send CRC protected data through SPI consists of these descriptors:
    1. Initialize CRC settings (for example, write CRC seed to DWn_CRC_LFSR_CTL0).
    2. Calculate CRC of transmit data.
    3. Append post-processed CRC result to transmit data (according to the description above).
    4. Transfer data to SCB TX FIFO.

Shared CRC unit / Mutual exclusive CRC calculations

There is only one single CRC register set per P-DMA instance, which holds the state and the settings for a CRC calculation. To prevent corruptions, a channel with an active CRC calculation must not be preempted by another channel executing a CRC descriptor before the post-processed CRC result from DWx_CRC_REM_RESULT0 has been backed-up or evaluated by the user.

Following possibilities exist:

  • Arbitrate the usage of the CRC unit through SW (only setup and trigger a new CRC calculation after the last one has completed and the result has been evaluated).
  • Implement the following solution that relies on HW mechanisms:
    • Disable preemption for the channels performing CRC calculations or assign them the same channel priority
    • Initialize all relevant CRC control registers as part of the descriptor chain (at least the CRC seed value must be written to DWn_CRC_LFSR_CTL0 even if all channels involved in CRC calculations use the same CRC standard)
    • The descriptor chain must also store the post-processed CRC result in SRAM after the CRC calculation has completed.
    • Ensure that the whole descriptor chain is executed by a single input trigger, otherwise another channel performing CRC calculations could become active during the individual trigger events.
0 Likes
Contributors