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TLI493D-A2B6 holds SDA low and the reset sequence mentioned in the User Manual doesn't work.

TLI493D-A2B6 holds SDA low and the reset sequence mentioned in the User Manual doesn't work.

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Community Translation: TLI493D-A2B6がSDA をlowに保持し、ユーザーマニュアルで記載されているリセットシーケンスが機能しません。

Question:
TLI493D-A2B6 holds SDA low, Reset sequence in User Manual doesn't work.
"Sometimes, I am unsure if its at power-up or during operation, the device pulls the SDA line low. According to the I2C standard,: “ If the data line (SDA) is stuck LOW, the master should send nine clock pulses. The device that held the bus LOW should release it sometime within those nine clocks." When we try this reset sequence the device keeps the SDA line LOW.
We then tried to send the reset sequence described in the device user manual, see section 2.3 “Sensor reset by I2C”. However, since the SDA line is held low by the device and the microcontroller try to send 0xFF, we are in an unknown state.
What do you recommend to get the device release the SDA line?"

Solution:
Let’s have a look at the conditions that can cause a SDA stuck low condition:
- No reset at device startup because of slow VDD ramp. A I2C reset sequence as described in the user manual forces the reset and frees the SDA pin (reset also works with SDA=low because 0x00 means SDA is low anyway)
- Aborted communication while sensor is outputting data (read command or ACK). The sensor state machine will wait for clocks to release SDA which is solved by the 0xFF of the reset sequence

We highly recommend to speed up the VDD ramp (directly connect to microcontroller high current GPIO or use transistor) to have a proper reset at startup, especially. There is the risk that SCL is stuck low at startup and this cannot be solved by the interface reset. In the datasheet there are two voltage limits defined:
- ADC restart level: if the voltage drops below the ADC restart level the current ADC conversion is stopped and restarted once the voltage is again above the restart level (+ hysteresis).
- Register stable level: if the voltage drops below the register stable level the configuration is lost and can be detected via the parity bits. A reset sequence and configuration cycle is required afterwards.

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