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SEMPER™ NOR Flash: Adaptive SPI clock speed in Linux and U-Boot - KBA238292

SEMPER™ NOR Flash: Adaptive SPI clock speed in Linux and U-Boot - KBA238292

Infineon_Team
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Since Linux 5.11 and U-Boot 2021.10, Linux and U-Boot MTD support the Infineon SEMPER™ Flash family. The SPI NOR framework in Linux and U-Boot MTD utilizes the Serial Flash Discoverable Parameter (SFDP) and flash configuration registers to setup the driver and flash.

The SFDP and configuration registers are read by the Read SFDP (opcode: 5Ah) and Read Any Register (opcode: 65h) transactions, respectively. The Read SFDP and Read Any Reigster transactions require latency cycles before flash outputs the data. Table 1 shows the relationship between default latency cycles and the maximum clock speed supported by the given latency cycles.

Table 1 Latency cycles and maximum clock speed

Transaction name

Opcode

Latency cycles used by MTD

Max clock speed
S25HL-T/S25HS-T

Max clock speed
S28HL-T/S28HS-T

Read SFDP

5Ah

3

50 MHz

166 MHz

Read Any Register (1S-1S-1S) *

65h

0

50 MHz

50 MHz

Read Any Register (8D-8D-8D) *

65h

3

-

25 MHz

* for volatile register read

 

The Linux and U-Boot MTD use those default latency cycles, and in some cases the clock speeds are limited to 50 MHz or 25 MHz. By default, the SPI host controllers are configured to a higher clock speed than 50 MHz for better performance. Modern SPI host controllers support high-speed Quad and Octal Flash operations with a configurable SPI clock output.

In the device driver for the SPI host controllers, the Opcode being issued can be checked, and the SPI clock speed can be lowered temporarily for specific Opcodes such as 5Ah and 65h.

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