Community Translation: CTI信号 (「CPU停止」など ) をTRAVEO™ T2Gトリガマルチプレクサへルーティング – KBA235072
Version: **
The Arm® CoreSight Cross Trigger Interface (CTI) supports the routing of debug related signals across the various CPU cores. Additionally, there are general-purpose CTI trigger input signals CTI_TR_IN[x] and general-purpose CTI trigger output signals CTI_TR_OUT[x] which are connected to the TRAVEO™ T2G trigger multiplexer where all MCU trigger signals are available. This can support use cases like requesting a CPU to halt execution on a certain system event, or to pause peripherals (e.g., TCPWM) if a CPU is currently halted. For the latter case, a “CPU halted” signal needs to be routed to the TRAVEO™ T2G trigger multiplexer where further configuration/processing will be needed (which will not be in the scope of this Knowledge Base Article).
The Arm® CoreSight debug infrastructure in TRAVEO™ T2G comprises multiple CTIs, one for each CPU core (e.g., CM4_CTI) and one common CTI (TRC_CTI). The TRC_CTI, along with the CPU-specific CTIs, provides the general-purpose CTI trigger input/output signals, which are connected to the TRAVEO™ T2G trigger multiplexer. For a complete list of all trigger input and output signals of all the CTIs, see the “Embedded Cross-Triggering” section of the TRAVEO™ T2G architecture reference manual.
All CTI trigger input and output signals can be connected to any of the four available Cross Trigger Matrix (CTM) channels in order to create a connection between a trigger input signal and a trigger output signal.
Example code to connect the “CM4 halted” signal to the CTI_TR_OUT[0] signal:
#define TRC_CTI_BASE 0xE0080000UL
#define TRC_CTI_REG__CTICONTROL (*((volatile uint32_t*)(TRC_CTI_BASE + 0x00)))
#define TRC_CTI_REG__CTIINEN(trigin_idx) (*((volatile uint32_t*)(TRC_CTI_BASE + 0x20 + 4*trigin_idx)))
#define TRC_CTI_REG__CTIOUTEN(trigout_idx) (*((volatile uint32_t*)(TRC_CTI_BASE + 0xa0 + 4 * trigout_idx)))
#define TRC_CTI_TRIGIN_IDX__CM0PLUS_HALTED 0
#define TRC_CTI_TRIGIN_IDX__CM4_HALTED 4
#define TRC_CTI_TRIGIN_IDX__CM7_0_HALTED 4
#define TRC_CTI_TRIGIN_IDX__CM7_1_HALTED 5
#define TRC_CTI_TRIGOUT_IDX__CTI_TR_OUT0 6
#define TRC_CTI_TRIGOUT_IDX__CTI_TR_OUT1 7
// TRC_CTI registers are only accessible if a debugger is connected
if(CPUSS->unDP_STATUS.stcField.u1SWJ_CONNECTED != 0)
{
// Enable TRC_CTI
TRC_CTI_REG__CTICONTROL = 1;
// Route "CM4 halted" input trigger signal to CTM channel #0
TRC_CTI_REG__CTIINEN(TRC_CTI_TRIGIN_IDX__CM4_HALTED) = 1;
// Route CTM channel #0 to "CTI_TR_OUT[0]" output trigger signal
TRC_CTI_REG__CTIOUTEN(TRC_CTI_TRIGOUT_IDX__CTI_TR_OUT0) = 1;
}
Notes:
The TRC_CTI registers can be accessed only by the Cortex®-M4 or Cortex®-M7 #0 (CM7_0), respectively. However, these CPUs can establish the required configurations that may be needed by the application software running on the other CPU cores (Cortex®-M0+ or Cortex®-M7 #1).
Furthermore, the registers are only accessible if a debugger is connected. Software can check the debugger connection status as shown in the example code.
The detailed information about the Arm® CoreSight Cross Trigger components (e.g., functional and register descriptions), see the Arm® website.
