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Resolving the error: “Unable to pack the design into available UDBs” - KBA233032

Resolving the error: “Unable to pack the design into available UDBs” - KBA233032

Chelladurai
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Resolving the error: “Unable to pack the design into available UDBs” - KBA233032

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When building a PSoC Creator project that uses UDBs, you may get the error “Unable to pack the design into available UDBs”. This error occurs when the synthesis tool cannot route and place all UDBs used in the design. To view the current UDB resource utilization, click the Resource Meter tab on the left of the PSoC Creator window, as seen in the image below.

Figure 1: Resource Meter Tab

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This error may occur even when the UDB resources have not been utilized completely. As seen in Figure 1, the error is observed when the UDB resource utilization is only 76 percent. To understand this, it is necessary to understand the UDB architecture and routing and placement tool. The router and placement algorithms are never 100 percent efficient to use up all areas.

A UDB consists of two “12C4” programmable logic devices (PLD). A PLD has 12 inputs, which feed across eight product terms (PT) in the AND array. In a given product term, the true (T) or complement (C) of the input can be selected. The output of the PTs are inputs into the OR array.

Figure 2: PLD 12C4 Structure from TRM

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The system should be designed such that it uses the resources optimally. The PLD architecture contains PTs; if a particular output uses more number of inputs to the block and corresponding PTs, then other macrocells and PTs may not be used in this PLD. This is because the tool is not able to find routes for all of the logic, due to the densely packed design. If the placer cannot find a complete block for the logic under consideration it may use a new PLD. For example, it is inefficient to use all the inputs for a particular PLD to generate only one output. This would mean the remaining AND, OR gates are unused when generating one out of four possible outputs from the macrocell (MC). Thus, a high number of inputs and a low number of outputs increases this inefficiency.

To understand the detailed PLD placement summary view the report file associated with a project. The report file is present in the Results tab of the Workspace Explorer as shown in the image below.

Figure 3: Viewing the project.rpt File

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The report file contains details regarding the number of PLDs used in a project and the average input, product terms, and macrocells used per PLD.

Figure 4: PLD Packing Summary

 

Chelladurai_3-1624531647657.pngIt also contains a digital placement section, which shows the blocks/instances that could not be placed. You can see the inputs and outputs in each PLD to have a better understanding.

Figure 5: Digital Placement Section

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Here are some possible solutions to resolve this issue:

  1. Use fixed-function blocks in your design. If possible, replace some UDB components with fixed-function blocks.
  2. Identify the cause of the issue by removing and adding back blocks.
  3. Analyze the component placement and force the placement to a cell.
    If you have a known working placement, you may be able to use it by adding a control file to the TopDesign component. To add the control file, right-click on the Top-Design component in the Components tab and click Add Component Item > Control File
    Use the -.fftgenctrlfile argument in Build Settings > Fitter to export a control file after successful placement in codegentemp/cyp3fit_results.ctl.

    For more details about adding a control file to your project, refer to the following documents:

  4. Confirm whether all the configurations of the component are required. For example, if using UART Tx only, do not configure the UART component as duplex or full-duplex mode.
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