Relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode
Question: What is the relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode?
In asynchronous mode (i.e with the FIFO's enabled FIFOBYP* = HIGH):
REFCLK is the clock used: 1. by the transmit PLL, it is the character clock and is multiplied up to become the bit clock and, 2. by the receive PLL, to keep it in or around lock when there is no serial data stream.
TXCLK and RXCLK are the clocks associated with the t/x and r/x FIFO's respectively. They are the clocks that clock the data in to and out of the respective FIFO's. These FIFO clocks can run at any speed from DC to 50 MHz and do not need to be at the same frequency as REFCLK. What you do need to consider however is that: 1. you must not write to the t/x FIFO faster than the data can be transmitted serially (this will eventually lead to FIFO overflow), unless managed by an external switching element, and, 2. you must read from the receive FIFO faster than it will fill up so as to avoid overflow i.e. if it fills up faster than you read from it it will overflow.
You must also avoid underflow situations (where you are reading data from an empty FIFO on the r/x side) as this will lead to garbage data. On the t/x side if the FIFO is empty K28.5's will pad the serial stream and you can delete these or use them at the receive side depending on what you want to do using the receiver dicard policies (see datasheet for more details).