Community Translation: QSPI NOR flash: モードビット使用に関する特別な考慮事項 – KBA235169
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Mode bits allow a series of single/dual/quad I/O SDR/DDR Read commands to eliminate the 8-bit instruction after the first command by sending a complementary mode bit pattern when repeating the same type of read command. This enables continuous read, which dramatically reduces initial access times and improves eXecute in Place (XIP) performance.
Infineon® NOR flash supports the mode bits in some read instructions to enable the continuous read operations. The mode bits patterns vary for different NOR flash families. See the following table for more information.
Table 2 Valid mode bits patterns for continuous read operation in QSPI NOR flash series
|
Operation name |
Instruction code |
Valid mode bits patterns for continuous read operations |
||
|
S25HL/HS-T |
S25FL/FS-S |
S25FL-L |
||
|
SDR Fast Read |
0Ch |
Axh |
Not supported |
Not supported |
|
SDR Dual I/O Read |
BBh / BCh |
Axh |
Axh |
Axh |
|
SDR Quad I/O Read |
EBh /ECh |
Axh |
Axh |
Axh |
|
DDR Quad I/O Read |
EDh / EEh |
A5h |
Upper and lower nibbles are complementary such as 5Ah, F0h |
Upper and lower nibbles are complementary such as 5Ah, F0h |
Figure 1 shows an example of the mode bit position in the Quad I/O SDR Read command sequence transitioning through the SPI signal bus.
Figure 1 Quad I/O SDR Read command sequence with mode bits
If the QSPI controller on SoC/MCU does not support mode bits output, the mode bits can be derived from or considered as part of the dummy bits. But if the QSPI controller does not drive the IOs in the dummy phase, we still have the corner case which can trigger the continuous read operation unexpectedly.
Assume that the QSPI controller of your SoC/MCU only toggles the SCK for dummy cycles but keeps the IOs frozen at their previous state after sending out the address in the Quad I/O SDR Read command.
As shown in Figure 2, if the host output address is 0xXXXX_XXXA, then the IOs are in the HIGH impedance state; the last 4-bit 1010b on IO3-0 move on to the next clock phase before changing their logical HIGH or LOW state; the NOR flash samples the residual 1010b as “Axh”. This is considered as a hit for the valid mode bits pattern and suddenly enters the continuous read mode unexpectedly. If the controller sends the following read transactions and still contains the 8-bit instruction, it causes read or boot issues.
Figure 2 Corner case to trigger continuous read in Quad I/O SDR Read command sequence
Do the following to avoid the corner case, if your QSPI controller cannot drive the mode bits:
- Use the aligned address (e.g., 16-byte) during reading especially for Quad I/O SDR Read operations. This avoids the 1010b pattern in the last 4 bits of address.
- Use Issue Mode Bit Reset (FFh) command or Software Reset (66h-99h) command either before or after each read command transaction to completely disable the continuous read feature if it was inadvertently enabled.