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Procedure of ECC error Injection to TC3x SRAM

Procedure of ECC error Injection to TC3x SRAM

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In this method we will change the data of SRAM but keep the ECC unchanged or change the ECC but keep the data unchanged. For both the cases, if we make a read access of that data then ECC will not match with the data and as a result an ECC error will occur. Both single bit and double bit error can be generated by the same method.

It is possible to inject a fake ECC error into SRAM by the following steps. In the following example we changed the SRAM data leaving corresponding ECC unchanged. The following example is a case of single bit ECC error. Double bit error can also be generated by the same way.

  1. First ensure ECCS.CENE bit is set and ECCD.CERR bit is clear.
  2. Set ALMSRCS.SBE = 1 to enable Single-Bit Error Notification and Tracking.
  3. Write 0x00000000 to an address (e.g. 0x70000000) in CPU0 DSPR
  4. Set MCi_ECCS.ECCMAP = 01. This will allow to change the data only leaving ECC unchanged.
  5. Write 0x00000001 to the address(0x70000000) in CPU0 DSPR. This will change 1 bit in this data.
  6.  Set MCi_ECCS.ECCMAP = 00. Back to normal mode.
  7. Read 32bit data from the address(0x70000000) in CPU0 DSPR. A single-bit error will be generated here. The error status bit and the address can be detected from the MCi_ECCD and MCi_ETRR registers.
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