Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob

PSoC 6 Serial Memory Interface (SMIF) Part 1

PSoC 6 Serial Memory Interface (SMIF) Part 1

Not applicable

Hi everyone!


The first device in the PSoC 6 portfolio, the PSoC 63 Connectivity line has up to 1MB of internal flash memory and 288 kB of internal SRAM. These memory resources can be used for code and variable storage. But when there is a need for a design to expand beyond the limits of internal memory resources, the user can interface an external memory device to supplement the internal resources. This can be achieved by the use of Serial Memory InterFace (SMIF) block in PSoC6.

The SMIF block is designed to interface through a SPI based interface. The SMIF block supports the following interfaces

  • Simple SPI interface. This is the most common interface covering memories of different types.
  • Dual SPI interface. Similar to SPI but with two data lines carrying two data bits at a time thus achieving twice the data rate of SPI
  • Quad SPI interface: This is a popular interface for Flash memory vendors recently. There are many flash memory devices in the market that support this interface. This interface has four data lines and hence can achieve a data rate that is four times that of the simple SPI
  • Octal SPI interface: This is a fairly new standard and memory manufacturers are starting to create devices supporting this interface. This interface will achieve 8 times the data rate of the normal SPI.
  • Dual-Quad SPI: in this mode of operation there are two Quad SPI memories interfaced with the PSoC 6. The two Quad SPI memories implement the two nibbles in a byte thus contributing to the entire byte. This mode can achieve the bit rate similar to the Octal SPI using two Quad SPI devices. Note that the data in the two Quad SPI memories are in nibble format.


The SMIF block in PSoC can interface up to four memory devices at a time. These memories devices can be of different types (Flash, RAM, NVSRAM, FRAM etc) and supporting different interfaces (SPI, Dual SPI, Quad SPI, Octal SPI). In addition to the interface capability, the SMIF block also supports two modes of operation.

  • Command mode (aka MMIO mode) where the SMIF block is treated as raw communication hardware. In this mode the communication over the SMIF interface(s) is effected by sending commands to the SMIF hardware. These are commands to transmit, receive and create dummy cycles on the different slave interfaces. The SMIF driver will have API to assist the user to create the command format needed for a memory device.
  • Memory mapped mode (aka XIP mode) where the memory devices interfaced with SMIF can be mapped into an internal memory address. This mode will need the user to configure the memory read/write command formats during initialization. The user can map all four interfaced memory devices to internal memory addresses. Any access to the internal addresses is automatically converted to SPI transactions by the SMIF block. Since the memory mapped mode implements both read and write transactions, a user can interface an external RAM memory to the SMIF interface and seamlessly use it as a part of the System RAM.


Feel free to leave comments or ask questions, we appreciate the feedback!