PSOC™4 HV PA: SWD LISTEN WINDOW - KBA237576
The PSoC™ 4 HVPA Program and Debug interface uses the SWD interface as the communication protocol with the external device.
The SWD listen window of PSoC™ 4 HVPA is a time window starting from the end of the system boot code (SROM boot). After the SROM boot completes, the CPU waits up to the time of the SWD listen window for a special connection sequence on the SWD port. If, during this time, the external SWD host device sends the correct sequence of SWD commands, the CPU enters Test mode for programming and debugging. Otherwise, the CPU moves to normal operation.
The default time of the listen window of the PSoC™ 4 HVPA is 24000 IMO cycles. For example, if IMO is 24 MHz, the listen window will be 1000 µs.
For more details, see the PSoC™ 4 HVPA-144K registers technical reference manual. Contact your local Infineon sales representative for access to the document.
Note: This KBA applies to the following series of PSoC™ 4 HV family MCUs:
- PSoC™ 4 HVPA series