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PLL Clock Jitter Impact on CAN Precision in TRAVEO II Family MCU – KBA233420

PLL Clock Jitter Impact on CAN Precision in TRAVEO II Family MCU – KBA233420

ArunKumarChoul
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Question: How do I evaluate the impact of PLL jitter on CAN precision when PLL clock is used for a CAN peripheral?

Answer: Use the following equation to evaluate the impact of PLL jitter on CAN precision:

ArunKumarChoul_1-1623906460410.png

 

Where,

  • tjitter.png = The specified PLL clock jitter as the absolute interval (CAN PLL jitter provided in product datasheet)
  • NBT = Nominal Bit Time (the inverse of a given CAN bit rate)
  • 10 = Maximum bit length during resynchronization guaranteed by bit stuffing in the case of no electrical disturbance. The case where 5-bit dominant continues and 5-bit recessive continues is 10-bit, which is the worst case during normal communication.

The result of dfjitter is the MCU drift equivalent and should be added to the oscillator drift value of the crystal or resonator as shown below:

dftotal = dfjitter + dfoscillator


Below shown is an example to verify whether the PLL clock of CYT2B7 Series meets the CAN precision specification.

Example:

  • CAN bit rate = 1 Mbps
  • PLL Jitter = ±0.75 ns (from PLL Specifications SID345A in the CYT2B7 Series Datasheet)
  • Drift of External Crystal Oscillator (ECO):  dfoscillator  = ± 0.01% (generally provided by the crystal supplier)
  • Allowed CAN node frequency tolerance: df = ± 0.01%

The 1 Mbps bit rate results in NBT = (1/1 Mbps) = 1 µs. The relative PLL Jitter interval ±0.75 ns results in an absolute interval tjitter  = ± 1.5 ns.

ArunKumarChoul_6-1623908878766.png

Therefore, the CAN PLL jitter specification of CYT2B7 meets the CAN specification.

Note: This KBA applies to the following series of TRAVEO II MCUs:

  • CYT2 Series
  • CYT3 Series
  • CYT4 Series

 

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