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Knowledge Base Articles

Optimize CapSense CSD Signal in Firmware - KBA226833


Optimize CapSense CSD Signal in Firmware - KBA226833

Author: RyanZ_36          Version: **

Translation - Japanese: CapSense CSD信号の最適化 - KBA226833 - Community Translated (JA)


When I tune the CapSense® sensor, raw count is low, what can I do to optimize raw count in firmware?


To optimize the touch signal, you need to update the parameters that directly influence the raw count. According to raw count equation 3-93-103-11 and 3-12 in AN85951, you can obtain ideal diff count equations when touch down, shown as following:


   CF is the finger capacitance. The following table provides the CapSense Component parameters as listed in Table 3-1 in AN85951.





Scan resolution

Increasing the scan resolution can increase the finger touch signal. Because the CapSense Component will take more charge/discharge cycles on sensors to sample more raw count after N is increased, the scanning time will also increase.


Internal reference voltage

For IDAC sourcing mode, increasing the internal reference voltage will increase the finger touch signal; for IDAC sinking mode, increasing it will decrease touch signal. Note that VREF must be in 1.2 V ~ (VDD–0.6) V.


Sense Clock Frequency

Increasing the sense clock frequency will increase the finger touch signal. However, if the sense clock is too fast, it may lead to insufficient charge and discharge of CapSense sensors. Read Sense Clock Related Parameters in AN85951 for more details.


Modulator IDAC

Increasing the modulator IDAC current will decrease the finger touch signal. Pay attention to its influence on raw count and baseline. Increasing the modulator IDAC will decrease the raw count. Baseline will follow the changes in raw count under the effect of the filters.


Compensation IDAC

Changing the compensation IDAC current will not change finger touch signal directly; however it can change the raw count slope and offset on the CS Axis. Figure 5-12 in AN85951 explains the relationship between raw count and Compensation IDAC.


Supply voltage

For IDAC sourcing mode, if VDD is always higher than VREF+0.6V, it will not have any influence on the raw count and signal. For IDAC sinking mode, changing VDD will change the signal as per Equation (2) and (4).

Note: This KBA summarized the influence on raw count and signal by changing CapSense parameters. However, you must consider other side effects such as changes in IDAC causing the raw count and baseline saturation, which will lead to low sensitivity of sensors. Contact sales and tech support team for more details.

Reference Document:

AN85951 - PSoC® 4 and PSoC® 6 MCU CapSense® Design Guide

Version history
Revision #:
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Last update:
‎Apr 01, 2019 02:27 AM
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