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OPTIREG™ TLF35584: Vs ramp-down behavior - KBA236970

OPTIREG™ TLF35584: Vs ramp-down behavior - KBA236970

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Community Translation: OPTIREG™ TLF35584: 対ランプダウン動作 - KBA236970

Version: **

This KBA discusses the ramp-down behavior of the input power supply voltage (Vs) of OPTIREG™ TLF35584 using four cases. All cases obey the following conditions:

  •  Vs is below the undervoltage reset threshold (VRT, XXX, low)
  • Above the power down threshold (Vpd_lo) without the boost pre-regulator in use

Note:   The buck pre-regulator cannot regulate to 5.8 V because the input voltage is already low. This drop in feedback voltage will cause the post regulator LDOs to go out of regulation when the feedback drops below 5 V from 5.8 V. This could trigger an undervoltage condition and possibly the StG on LDO rails.

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Figure  1  OPTIREG™ TLF35584QVVS1 – 5V Variant under Vs ramp down

  • Case 1: Vs below the undervoltage reset threshold (VRT, XXX, low) and above the power-down threshold, VPD_lo for t ≤  tRR (reset reaction time)

TLF35584 doesn’t assert the ROT signal; all regulators remain on. (See Figure 20 in the  
TLF35584 datasheet).

  • Case 2: Vs below the undervoltage reset threshold (VRT, XXX, low) and above the power-down threshold, (VPD_lo) for  tRR ≤ t ≤ tStG (short to ground)

The ROT signal is asserted, indicating an undervoltage event; TLF35584 moves to the INIT state. (See Figure 20 in the TLF35584 datasheet)

  • Case 3: Vs below the undervoltage reset threshold (VRT, XXX, low) and above the power-down threshold, (VPD_lo) for t ≥ tStG
    -Case 3.1: If Vquc continues to be in the undervoltage condition, but greater than the power-down threshold for t ≥ tStG, the device registers a failsafe event incrementing the FAILSAFE counter to ‘1’ and enters the FAILSAFE state for 20 ms.
    - Case 3.2: The PMIC tries to move out of the FAILSAFE state after a 20 ms to the INIT state, thereby restarting all regulators. If the regulators cannot regulate because of the low input voltage, it causes three other consecutive FAILSAFE events. After three successive FAILSAFE events, the device locks up in permanent FAILSAFE state because of QUC (µC related LDO) and can only be released by a Wake event on the WAK/ENA pin.
    - Case 3.3: If the Vs goes below the undervoltage reset threshold (VRT, XXX, low) and above the power-down threshold (VPD_lo) three times in a row (even if there is normal a voltage in between) will cause permanent FAILSAFE.
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Figure 2   Measurement results 1

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Figure 3   Measurement results 2

  • Case 4: Vs is below the power-down threshold (VpD_lo)

   - PMIC will move to power-down state. The device will restart when the input voltage ramps up. Make sure that the ramp-up is fast enough for the preregulator buck to regulate with load conditions in place.

Note:  VRT, XXX, low = Undervoltage reset threshold: VRT, VCI, low, VRT, QUC, low or VRT, QST, low

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